ISL6310EVAL1Z Intersil, ISL6310EVAL1Z Datasheet - Page 22

• Manufacturer Part Number: ISL6310EVAL1Z
• Description: EVALUATION BOARD FOR ISL6310
• Manufacturer: Intersil

Specifications of ISL6310EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 60A
• Voltage - Input: 5 ~ 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

and C
locating the poles and zeros of the compensation network:
1. Select a value for R
2. Calculate C
FIGURE 22. VOLTAGE-MODE BUCK CONVERTER
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R
multiplied by a factor of (R
of the calculations remain unchanged, as long as the
compensated R
R
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
C
CIRCUIT
2
1
3
PWM
) in Figures 20 and 21. Use the following guidelines for
=
=
-------------------------------------------- -
d
---------------------------------------------- -
2π R
V
MAX
COMP
OSC
⋅
COMPENSATION DESIGN
2
1
2
⋅
HALF-BRIDGE
OSCILLATOR
V
such that F
for desired converter bandwidth (F
⋅
⋅
1
V
R
0.5 F
IN
OSC
E/A
DRIVE
1
2
⋅
⋅
LC
⋅
F
R
value is used.
F
ISL6310
LC
2
0
LC
1
(to adjust, change the 0.5 factor to
C
+
-
(1kΩ to 5kΩ, typically). Calculate
VREF
+
2
-
Z1
C
22
1
is placed at a fraction of the F
P1
FB
PHASE
UGATE
LGATE
+ R
VSEN
VDIFF
RGND
EXTERNAL CIRCUIT
2
CE
value needs be
S1
R
/F
)/R
3
V
LC
IN
R
P1
1
, the lower the F
LC
C
. The remainder
L
3
).
DCR
V
ESR
OUT
0
C
). If
(EQ. 30)
(EQ. 31)
LC
Z1
ISL6310
,
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 23 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 23 by adding the modulator gain,
G
G
F
F
F
F
3. Calculate C
4. Calculate R
Z1
P1
P2
Z2
MOD
MOD
G
G
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
FB
CL
C
R
C
=
=
=
=
2
3
3
f ( )
f ( )
f ( )
------------------------------ -
2π R
(in dB), to the feedback compensation gain, G
-------------------------------------------------
2π
-------------------------------------------- -
2π R
------------------------------ -
2π R
=
=
=
=
=
=
------------------------------------------------------- -
2π R
--------------------- -
F
----------- - 1
------------------------------------------------ -
2π R
⋅
F
⋅
⋅
⋅
SW
SW
(
LC
------------------------------------------------------------------------------------------------------------------------ -
(
G
1
d
----------------------------- -
--------------------------------------------------- - ⋅
s f ( ) R
R
1
R
2
1
2
3
⋅
⋅
MAX
1
MOD
1
1
⋅
⋅
⋅
V
+
1
). F
–
P2
C
+
+
1
-------------------- -
C
C
2
2
3
3
C
OSC
⋅
s f ( ) R
1
R
⋅
⋅
s f ( ) R
3
1
such that F
such that F
1
FB
1
C
SW
0.7 F
⋅
is placed below F
C
f ( ) G
1
3
+
⋅
V
1
) C
C
1
⋅
⋅
C
) and closed-loop response (G
IN
⋅
⋅
⋅
(
⋅
⋅
2
represents the per-channel switching
2
C
F
1
3
⋅
P2
2
3
CE
1
FB
SW
+
---------------------------------------------------------------------------------------------------------- -
1
⋅
⋅
+
C
s f ( )
+
C
against the capabilities of the error
f ( )
–
C
3
s f ( )
1
)
P1
1
Z2
2
⋅
)
⋅
⎛
⎜
⎝
(
1
is placed at F
is placed at F
⋅
R
(
+
1
CL
ESR
where s f ( )
+
s f ( ) R
1
SW
, is constructed on the
R
+
3
s f ( ) ESR C
+
⋅
) C
(typically, 0.5 to 1.0
DCR
⋅
,
P2
MOD
2
⋅
⋅
3
⎛
⎜
⎝
lower in frequency
CE
LC
-------------------- -
C
C
) C
), feedback
=
⋅
1
1
. Calculate C
.
+
⋅
⋅
2π f j
C
+
C
2
s
2
August 7, 2008
⋅ ⋅
CL
⎞
⎟
⎠
2
⎞
⎟
⎠
f ( ) L C
(EQ. 32)
(EQ. 33)
(EQ. 34)
(EQ. 35)
(EQ. 36)
(EQ. 37)
(EQ. 38)
):
FB
FN9209.4
⋅
(in
⋅
3