MAX15034BEVKIT+ Maxim Integrated Products, MAX15034BEVKIT+ Datasheet - Page 12

• Manufacturer Part Number: MAX15034BEVKIT+
• Description: KIT EVALUATION FOR MAX15034
• Manufacturer: Maxim Integrated Products

Specifications of MAX15034BEVKIT+

• Main Purpose: DC/DC, Step Down
• Voltage - Input: 5 ~ 28V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: MAX15034
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -
• Frequency - Switching: -
• Outputs And Type: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
The MAX15034 can operate as a dual-output, indepen-
dently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic-low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1), and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic-high), VEA2 is dis-
connected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
The MAX15034 accepts a wide input voltage range at
IN of 5V to 28V. An internal linear regulator steps down
V
The output of this regulator is available at REG. For V
= 4.75V to 5.5V, connect IN and REG together external-
ly. REG can supply up to 65mA for external loads.
Bypass REG to AGND with a 4.7μF ceramic capacitor
for high-frequency noise rejection and stable operation.
REG supplies the current for the MAX15034’s internal
circuitry and for the MOSFET gate drivers (when con-
nected externally to V
Calculate the maximum bias current (I
MAX15034:
where I
typ), Q
charges of MOSFETs Q1 through Q4 at V
Figure 6), and f
individual phase.
V
vers. Connect the regulator output REG externally to
V
and a parallel combination of 1μF and 0.1μF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
Connect BST1 and BST2 to V
diodes D1 and D2 (see Figure 6). Connect a 0.1μF
ceramic capacitor between BST_ and LX_.
12
IN
DD
DD
I
BIAS
to 5.1V (typ) and provides power to the MAX15034.
______________________________________________________________________________________
Supply Voltage Connections (V
is the power input for the low-side MOSFET dri-
through an R-C lowpass filter. Use a 1Ω resistor
High-Side MOSFET Drive Supply (BST_)
Dual-Output/Dual-Phase Select (MODE)
Low-Side MOSFET Driver Supply (V
IN
GQ1
=
I
is the quiescent supply current into IN (4mA,
IN
, Q
+
f
SW
GQ2
SW
×
, Q
is the switching frequency of each
(
Q
DD
GQ
GQ3
), and can source up to 65mA.
1
+
, Q
Q
GQ
GQ4
2
DD
+
are the total gate
Q
through rectifier
GQ
3
BIAS
GS
+
IN
Q
= 5V (see
GQ
) for the
/V
4
REG
)
DD
IN
)
)
Minimize the trace inductance from BST_ and V
the rectifier diodes, D1 and D2, and from BST_ and LX_
to the boost capacitors, C8 and C9 (see Figure 6). This
is accomplished by using short, wide trace lengths.
The MAX15034 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output volt-
age. The UVLO threshold monitors V
nally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates chattering during
startup. Most of the internal circuitry, including the
oscillator, turns on when V
MAX15034 draws up to 4mA (typ) of current before
V
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6). The voltage at the current-
error amplifier output limits the maximum current avail-
able to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus, the output voltage.
An internal oscillator generates the 180
clock signals required for both PWM modulators. The
oscillator also generates the 2V
essary for the PWM comparators. The oscillator fre-
quency can be set from 200kHz to 2MHz by an external
resistor (R
Figure 6). The equation below shows the relationship
between R
where R
quency is f
Use RT/CLKIN as a clock input to synchronize the
MAX15034 to an external frequency (f
Applying an external clock to RT/CLKIN allows each
PWM section to work at a frequency equal to
f
old detects f
logic switches from the internal oscillator clock, to the
clock present at RT/CLKIN.
RT/CLKIN
REG
reaches the UVLO threshold.
Setting the Switching Frequency (f
RT
/2. An internal comparator with a 1.6V thresh-
T
T
SW
is in ohms and the per-phase switching fre-
) connected from RT/CLKIN to AGND (see
and the switching frequency:
RT/CLKIN
Power-On Reset (POR)/Soft-Start
= f
f
OSC
Undervoltage Lockout (UVLO)/
OSC
=
/2.
. If f
2 5 10
.
R
×
RT/CLKIN
RT
REG
10
P-P
Hz
reaches 4.5V. The
voltage ramps nec-
is present, internal
REG
o
out-of-phase
and is inter-
RT/CLKIN
DD
SW
to
).
)