DK86060-3 Fujitsu Semiconductor America Inc, DK86060-3 Datasheet - Page 24

• Manufacturer Part Number: DK86060-3
• Description: KIT DEV 16BIT DAC FOR MB86060
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86060-3

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 400M
• Data Interface: Parallel
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1009

Power supply tracks should be kept as short and wide as possible. The ground and supply tracks
should run adjacent to each other for as far as possible, whilst avoiding all signal tracks that may
couple noise into the supply.
4.3
All supplies and references should be decoupled to the appropriate ground plane using surface
mount 100nF capacitors, placed as close as possible to the device. For each pair of VDD/VSS pins
it is recommended that the capacitor is located on the reverse of the PCB, immediately under the
device, with vias to the supply and ground planes as close as physically possible to the device and
capacitor. This layout minimizes the total length of track, including the plated through hole, and hence
keeps loop inductance to a minimum. An example of the recommended layout, using 0603 format
surface mount capacitors and a four layer PCB is illustrated in figure 13.
Page 24 of 44
Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Decoupling
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
SHUF0
SHUF1
TWOC
DITH0
DITH2
DSUB
OVER
FILTS
RVSS
BGAP
RREF
DITH1
FILTF
VREF
ASUB
VDD
VDD
VSS
VSS
N/C
N.B. Not to scale. All vias connect to the appropriate Ground or Power plane.
Figure 13 Recommended Supply Decoupling Layout
Pin #1
MB86060 16-bit Interpolating Digital to Analog Converter
Production
Copyright © 2003-2009 Fujitsu Microelectronics Europe GmbH
February 2009 Version 2.0
Layer 1 pads
Layer 4 pads
FME/MS/SFDAC1/DS/4250
MUL0
MUL1
MUL2
VSS
VDD
CKOUT
CKOUTB
VSS
VDD
DSUB
LOCK
CSUB
NSHAPE
CLKSEL
RESETB
CVDD
CVSS
CLK
CVSS
CLKB