ADIS16240/PCBZ Analog Devices Inc, ADIS16240/PCBZ Datasheet - Page 9

• Manufacturer Part Number: ADIS16240/PCBZ
• Description: BOARD EVAL FOR ADIS16240
• Manufacturer: Analog Devices Inc
• Series: iMEMS®, iSensor™r

Specifications of ADIS16240/PCBZ

• Sensor Type: Accelerometer, 3 Axis
• Sensing Range: ±19g
• Interface: SPI Serial
• Sensitivity: 51.4mg/LSB
• Voltage - Supply: 2.4 V ~ 3.6 V
• Embedded: No
• Utilized Ic / Part: ADIS16240
• Silicon Manufacturer: Analog Devices
• Application Sub Type: Shock Sensor
• Kit Application Type: Sensing - Motion / Vibration / Shock
• Silicon Core Number: ADIS16240
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

BASIC OPERATION
The ADIS16240 starts up automatically when it has a valid power
supply and begins producing digital acceleration data in the output
registers. When using the factory-default configuration, DIO1
serves as a data-ready indicator signal that can drive a processor
interrupt function. Figure 14 shows a schematic for connecting
to a SPI-compatible processor platform, referred to as the SPI
master.
Table 5. Generic Master Processor Pin Names and Functions
Pin Name
SS
IRQ1, IRQ2
MOSI
MISO
SCLK
The ADIS16240 SPI interface supports full duplex serial commu-
nication (simultaneous transmit and receive) and uses the bit
sequence shown in Figure 18. Processor platforms typically support
SPI communication with general-purpose serial ports that require
some configuration in their control registers. Table 6 lists the most
common settings that require attention when initializing a pro-
cessor serial port for communication with the ADIS16240.
Table 6. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2.5 MHz
SPI Mode 3 (1,1)
MSB First
16-Bit
SYSTEM PROCESSOR
SPI MASTER
Figure 14. Electrical Hook-Up Diagram
V
DD
SCLK
MOSI
MISO
IRQ1
IRQ2
Description
The ADIS16240 operates as a slave.
Bit rate setting.
Clock polarity/phase (CPOL = 1, CPHA = 1).
Bit sequence.
Shift register/data length.
SS
Function
Slave select.
Interrupt request inputs.
Master output, slave input.
Master input, slave output.
Serial clock.
SCLK
DIN
CS
DIN = 0x0400 PRODUCES XACCL_OUT CONTENTS ON
DOUT DURING THE NEXT SPI SEGMENT
CS
SCLK
DIN
DOUT
DIO1
DIO2
ADIS16240
SPI SLAVE
SPI SEGMENT 1
V
DD
Figure 17. Example SPI Read Sequence
Rev. 0 | Page 9 of 16
DOUT
User registers govern all data collection and configuration. Table 7
provides a memory map that includes all user registers, along with
references to bit assignment tables that follow the generic assign-
ments in Figure 15.
SPI Write Commands
Master processors write to the control registers, one byte at a
time, using the bit assignments shown in Figure 18. The program-
mable registers in Table 7 provide controls for optimizing sensor
operation and for starting various automated functions. For
example, set GLOB_CMD[8] = 1 (DIN = 0xCB01) to wake up the
device.
Some configurations require writing both bytes to a register,
which takes two separate 16-bit sequences. See GLOB_CMD[3]
in Table 24 for backing up configuration data in nonvolatile
flash memory.
SPI Read Commands
Reading data on the SPI requires two consecutive 16-bit
sequences. The first sequence transmits the read command on
DIN, and the second sequence receives the resulting data from
DOUT. The 7-bit register address can represent either the upper
or lower byte address for the target register. For example, DIN
can be either 0x0200 or 0x0300 when reading the SUPPLY_OUT
register. The SPI operates in full duplex mode, which means that
the master processor can read the output data from DOUT while
using the same SCLK pulses to transmit a new command on
DIN. In Figure 17, the second SPI segment sets up the device to
read YACCL_OUT on the following SPI segment (not shown).
SCLK
15
DIN
CS
Figure 16. SPI Sequence for a Wake-Up Command (DIN = 0xCB01)
14
13
UPPER BYTE
DOUT = 0x802B = 2.21g, NEW DATA
12
Figure 15. Generic Register Bit Assignments
11
10
SPI SEGMENT 2
9
DIN = 0x0600 TO READ YACCL_OUT
8
7
6
5
LOWER BYTE
4
ADIS16240
3
2
1
0