DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 7

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Family Overview
Architecture Features
MultiTrack Interconnect
TriMatrix Embedded Memory Blocks
DSP Blocks
© March 2010 Altera Corporation
f
f
In the Stratix III architecture, connections between ALMs, TriMatrix memory, DSP
blocks, and device I/O pins are provided by the MultiTrack interconnect structure
with DirectDrive technology. The MultiTrack interconnect consists of continuous,
performance-optimized row and column interconnects that span fixed distances. A
routing structure with fixed length resources for all devices allows predictable and
repeatable performance when migrating through different device densities. The
MultiTrack interconnect provides 1-hop connection to 34 adjacent LABs, 2-hop
connections to 96 adjacent LABs and 3-hop connections to 160 adjacent LABs.
DirectDrive technology is a deterministic routing technology that ensures identical
routing resource usage for any function regardless of placement in the device. The
MultiTrack interconnect and DirectDrive technology simplify the integration stage of
block-based designing by eliminating the reoptimization cycles that typically follow
design changes and additions. The Quartus II Compiler also automatically places
critical design paths on faster interconnects to improve design performance.
For more information, refer to the
TriMatrix embedded memory blocks provide three different sizes of embedded
SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory
includes the following blocks:
■
■
■
Each embedded memory block can be independently configured to be a single- or
dual-port RAM, ROM, or shift register via the Quartus II MegaWizard
Manager. Multiple blocks of the same type can also be stitched together to produce
larger memories with minimal timing penalty. TriMatrix memory provides up to
16,272 Kbits of embedded SRAM at up to 600 MHz operation.
For more information about TriMatrix memory blocks, modes, features, and design
considerations, refer to the
chapter.
Stratix III devices have dedicated high-performance digital signal processing (DSP)
blocks optimized for DSP applications requiring high data throughput. Stratix III
devices provide you with the ability to implement various high-performance DSP
functions easily. Complex systems such as WiMAX, 3GPP WCDMA, CDMA2000,
voice over Internet Protocol (VoIP), H.264 video compression, and high-definition
television (HDTV) require high-performance DSP blocks to process data. These
system designs typically use DSP blocks to implement finite impulse response (FIR)
filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier
transform (FFT) functions, and discrete cosine transform (DCT) functions.
320-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers,
and shift registers
9-Kbit M9K blocks that can be used for general purpose memory applications
144-Kbit M144K blocks that are ideal for processor code storage, packet and video
frame buffering
TriMatrix Embedded Memory Blocks in Stratix III Devices
MultiTrack Interconnect in Stratix III Devices
Stratix III Device Handbook, Volume 1
TM
Plug-In
chapter.
1–7