DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 6

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–6
Table 1–5. Speed Grades for Stratix III Devices (Part 2 of 2)
Architecture Features
Logic Array Blocks and Adaptive Logic Modules
Stratix III Device Handbook, Volume 1
EP3SE260
Note to
(1) For EP3SL340, EP3SL200, and EP3SE260 devices, the industrial junction temperature range for –4L is 0–100°C, regardless of supply voltage.
Device
Table
Commercial
Industrial
Temperature
1–5:
f
f
Grade
(1)
The following section describes the various features of the Stratix III family FPGAs.
The Logic Array Block (LAB) is composed of basic building blocks known as
Adaptive Logic Modules (ALMs) that can be configured to implement logic,
arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains,
shared arithmetic chains, LAB control signals, local interconnect, and register chain
connection lines. ALMs are part of a unique, innovative logic structure that delivers
faster performance, minimizes area, and reduces power consumption. ALMs expand
the traditional 4-input look-up table architecture to 7 inputs, increasing performance
by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize
DSP performance with dedicated functionality to efficiently implement adder trees
and other complex arithmetic functions. The Quartus II Compiler places associated
logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
The Stratix III LAB has a new derivative called Memory LAB (or MLAB), which adds
SRAM memory capability to the LAB. MLAB is a superset of the LAB and includes all
LAB features. MLABs support a maximum of 320 bits of simple dual-port Static
Random Access Memory (SRAM). Each ALM in an MLAB can be configured as a
16×2 block, resulting in a configuration of 16×20 simple dual port SRAM block. MLAB
and LAB blocks always co-exist as pairs in all Stratix III families, allowing up to 50%
of the logic (LABs) to be traded for memory (MLABs).
For more information about LABs and ALMs, refer to the
Adaptive Logic Modules in Stratix III Devices
For more information about MLAB modes, features and design considerations, refer
to the
484 -Pin
FineLine
TriMatrix Embedded Memory Blocks in Stratix III Devices
BGA
—
—
FineLine
780-Pin
BGA
—
—
–3, –4, –4L
–2, –3, –4,
FineLine
780-Pin
Hybrid
BGA
–4L
–3, –4, –4L
1152-Pin
–2,– 3, –4,
FineLine
BGA
chapter.
–4L
Chapter 1: Stratix III Device Family Overview
1152-Pin
FineLine
Hybrid
BGA
—
—
Logic Array Blocks and
© March 2010 Altera Corporation
chapter.
1517-Pin
–2, –3, –4,
–3, –4,–4L
FineLine
BGA
–4L
Architecture Features
1760-Pin
FineLine
BGA
—
—