DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 11

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Family Overview
Architecture Features
Remote System Upgrades
IEEE 1149.1 (JTAG) Boundary-Scan Testing
Design Security
© March 2010 Altera Corporation
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Stratix III devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and transmit this
compressed bitstream to Stratix III devices. During configuration, the Stratix III
device decompresses the bitstream in real time and programs its SRAM cells.
Stratix III devices support decompression in the FPP when using a MAX II
device/microprocessor plus flash, fast AS, and PS configuration schemes. The
Stratix III decompression feature is not available in the FPP when using the enhanced
configuration device and JTAG configuration schemes.
For more information, refer to the
Stratix III devices feature remote system upgrade capability, allowing error-free
deployment of system upgrades from a remote location securely and reliably. Soft
logic (either the Nios embedded processor or user logic) implemented in a Stratix III
device can download a new configuration image from a remote location, store it in
configuration memory, and direct the dedicated remote system upgrade circuitry to
initiate a reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, and can recover from an error condition
by reverting back to a safe configuration image, and provides error status
information. This dedicated remote system upgrade circuitry is unique to Stratix
series FPGAs and helps to avoid system downtime.
For more information, refer to the
chapter.
Stratix III devices support the JTAG IEEE Std. 1149.1 specification. The Boundary-Scan
Test (BST) architecture offers the capability to test pin connections without using
physical test probes and capture functional data while a device is operating normally.
Boundary-scan cells in the Stratix III device can force signals onto pins or capture data
from pin or logic array signals. Forced test data is serially shifted into the
boundary-scan cells. Captured data is serially shifted out and externally compared to
expected results. In addition to BST, you can use the IEEE Std. 1149.1 controller for
Stratix III device in-circuit reconfiguration (ICR).
For more information, refer to the
Stratix III Devices
Stratix III devices are high-density, high-performance FPGAs with support for 256-bit
volatile and non-volatile security keys to protect designs against copying, reverse
engineering, and tampering. Stratix III devices have the ability to decrypt a
configuration bitstream using the Advanced Encryption Standard (AES) algorithm,
an industry standard encryption algorithm that is FIPS-197 certified and requires a
256-bit security key.
chapter.
Configuring Stratix III Devices
Remote System Upgrades with Stratix III Devices
IEEE 1149.1 (JTAG) Boundary Scan Testing in
Stratix III Device Handbook, Volume 1
chapter.
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