DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 10

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–10
Hot Socketing and Power-On Reset
Configuration
Stratix III Device Handbook, Volume 1
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4×, 6×, 7×, 8×, and 10× SERDES modes when using the dedicated DPA circuitry. DPA
minimizes bit errors, simplifies PCB layout and timing management for high-speed
data transfer, and eliminates channel-to-channel and channel-to-clock skew in
high-speed data transmission systems. Soft CDR can also be implemented, enabling
low-cost 1.6-Gbps clock embedded serial links.
Stratix III devices have the following dedicated circuitry for high-speed differential
I/O support:
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For more information, refer to the
Stratix III Devices
Stratix III devices are hot-socketing compliant. Hot socketing is also known as hot
plug-in or hot swap, and power sequencing support without the use of any external
devices. Robust on-chip hot-socketing and power-sequencing support ensures proper
device operation independent of the power-up sequence. You can insert or remove a
Stratix III board in a system during system operation without causing undesirable
effects to the running system bus or the board that was inserted into the system.
The hot-socketing feature makes it easier to use Stratix III devices on PCBs that also
contain a mixture of 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. With the
Stratix III hot socketing feature, you do not need to ensure a specific power-up
sequence for each device on the board.
For more information, refer to the
Devices chapter.
Stratix III devices are configured using one of the following four configuration
schemes:
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All configuration schemes use either an external controller (for example, a MAX
device or microprocessor), a configuration device, or a download cable.
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
Dynamic phase aligner (DPA)
Soft CDR functionality
Synchronizer (FIFO buffer)
PLLs
Fast passive parallel (FPP)
Fast active serial (AS)
Passive serial (PS)
Joint Test Action Group (JTAG)
chapter.
High Speed Differential I/O Interfaces with DPA in
Hot Socketing and Power-On Reset in Stratix III
Chapter 1: Stratix III Device Family Overview
© March 2010 Altera Corporation
Architecture Features
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