DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 13

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Family Overview
Reference and Ordering Information
Signal Integrity
Reference and Ordering Information
Software Support
© March 2010 Altera Corporation
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Stratix III devices simplify the challenge of signal integrity through a number of chip,
package, and board level enhancements to enable efficient high-speed data transfer
into and out of the device. These enhancements include:
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For more information about SI support in the Quartus II software, refer to the
Quartus II
For more information about how to use the various configuration, PLL, external
memory interfaces, I/O, high-speed differential I/O, power, and JTAG pins, refer to
the
The following section describes Stratix III device software support and ordering
information.
Stratix III devices are supported by the Altera Quartus II design software, version 6.1
and later, which provides a comprehensive environment for
system-on-a-programmable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full simulation and
advanced timing analysis, SignalTap
For more information about the Quartus II software features, refer to the
Handbook.
The Quartus II software supports a variety of operating systems. The specific
operating system for the Quartus II software can be obtained from the Quartus II
Readme.txt file or the
supports seamless integration with industry-leading EDA tools through the
NativeLink
8:1:1 user I/O/Gnd/V
Dedicated power supply for each I/O bank, limit of I/Os is 24 to 48 I/Os per bank,
to help limit simultaneous switching noise
Programmable slew-rate support with up to four settings to match desired I/O
standard, control noise, and overshoot
Programmable output-current drive strength support with up to six settings to
match desired I/O standard performance
Programmable output-delay support to control rise/fall times and adjust duty
cycle, compensate for skew, and reduce simultaneous switching outputs (SSO)
noise
Dynamic OCT with auto calibration support for series and parallel OCT and
differential OCT support for LVDS I/O standard on the left/right banks
Stratix III Device Family Pin Connection
Handbook.
®
interface.
Operating System Support
CC
ratio to reduce the loop inductance in the package
®
II logic analyzer, and device configuration.
Guidelines.
section of the Altera website. It also
Stratix III Device Handbook, Volume 1
Quartus II
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