HW-SD1800A-DSP-SB-UNI-G Xilinx Inc, HW-SD1800A-DSP-SB-UNI-G Datasheet - Page 19

• Manufacturer Part Number: HW-SD1800A-DSP-SB-UNI-G
• Description: KIT DEVELOPMENT SPARTAN 3ADSP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr
• Type: DSPr

Specifications of HW-SD1800A-DSP-SB-UNI-G

• Contents: Development Platform, Power Supply and software
• Silicon Manufacturer: Xilinx
• Features: 10/100/1000 PHY, JTAG Programming And Configuration Port
• Silicon Family Name: Spartan-3A
• Silicon Core Number: 3SD1800A-FG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Spartan 3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1574; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-SB-UNI-G

Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
R
RS232
SPI Expansion
Digilent Headers
Table 9: RS232 Signals
Table 10: SPI Connector (J10)
The auto-MDIX mode provides automatic swapping of the differential pairs. This allows
the PHY to work with either a straight-through cable or crossover cable. Use a CAT-5e or
CAT-6 Ethernet cable when operating at 1000 Mb/s (Gigabit Ethernet). The boundary-
scan Test Access Port (TAP) controller of the DP83865 must be in reset for normal
operation. This active low reset pin of the TAP (TRST) is pulled low through a 1K resistor
on the board.
The RS232 transceiver is a Texas Instruments MAX3221 device. This transceiver operates
at 3.3V with an internal charge pump to create the RS232 compatible output levels. The
RS232 interface is brought out on DB9 connector P2. This RS232 interface supports only
null-modem serial cables. A male-to-female serial cable should be used to plug J11 into a
standard PC serial port (male DB9).
interface.
A 0.1” 2 x 6 header (J10) provides an expansion of the FPGA SPI interface. In addition to
the SPI signals SPI_SEL#, SPI_CLK, SPI_MOSI and SPI_MISO, four additional SPI select
signals are provides (SPISEL_1, SPISEL_2, SPISEL_3, and SPISEL_4). All SPI select signals
have 4.7K pull-ups, SPI_CLK has a 4.7K pull-down. 3.3V power and Ground are also
provided on J10.
Two right-angle, 6 pin (1 x 6 female) Digilent headers (J6, J7) are provided on the Spartan-
3A DSP Starter Platform. Each header provides 3.3V power, Ground, and four I/Os. It has
the appearance of an SPI port, or can be used as 4 general purpose I/Os.
pinout of the Digilent headers;
FPGA Pin
Number
AD26
AC25
W20
W21
—
—
FPGA_RS232_Rx
FPGA_RS232_Tx
Net Name
Table 10
SPISEL_1
SPISEL_2
SPISEL_3
SPISEL_4
Signal
GND
3.3 V
www.xilinx.com
lists and describes the J10 connections.
Table 11
Number
J10 Pin
Table 9
10
12
2
4
6
8
provides the FPGA pinout.
Transmit data, TD
Receive data, RD
shows the FPGA pin-out for the RS232
Description
Number
J10 Pin
11
1
3
5
7
9
SPI_MOSI
SPI_MISO
SPI_SEL#
SPI_CLK
Signal
GND
3.3 V
Functional Description
FGPA Pin Number
Figure 6
N21
FPGA Pin
P22
Number
AE24
Ab15
AF24
shows the
AA7
—
—
43