HW-SD1800A-DSP-SB-UNI-G Xilinx Inc, HW-SD1800A-DSP-SB-UNI-G Datasheet - Page 28

• Manufacturer Part Number: HW-SD1800A-DSP-SB-UNI-G
• Description: KIT DEVELOPMENT SPARTAN 3ADSP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr
• Type: DSPr

Specifications of HW-SD1800A-DSP-SB-UNI-G

• Contents: Development Platform, Power Supply and software
• Silicon Manufacturer: Xilinx
• Features: 10/100/1000 PHY, JTAG Programming And Configuration Port
• Silicon Family Name: Spartan-3A
• Silicon Core Number: 3SD1800A-FG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Spartan 3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1574; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-SB-UNI-G

Configuration
Configuration
52
Table 17: EXP Connector JX2 Pinout (Cont’d)
The Spartan-3A DSP Starter Platform provides four mechanisms to program and configure
the FPGA; these are JTAG, parallel flash, serial flash, and the SystemACE Module (SAM).
The SAM configures the FPGA in Boundary Scan mode. The parallel Flash device may also
be programmed via the JTAG connector, but the Serial memory device must be
programmed through the J10 Header. The FPGA is the only device in the JTAG chain on
the Spartan-3A DSP Starter Platform. The serial Flash, Parallel Flash, and SystemACE are
described earlier in this document. Depending on the setting of configuration jumpers
M[2:0], any of these configuration options can be the source. Programming the Spartan-3A
DSP via Boundary Scan requires that a JTAG download cable be attached to one of two
interfaces that are wired in parallel on the board as shown in
can be attached to either the 14-pin 2mm spaced header (J2) with a ribbon cable or to the
0.1” header (J4) with flying leads. If the Xilinx Parallel Cable IV is used, the ribbon cable
connector mates with the keyed J2 connector. The Xilinx Platform USB cable will also mate
directly with J2.
Pin No.
FPGA
AA10
AE14
AC9
AB9
AF5
AE6
Y10
V11
U11
W9
Y9
-
-
-
-
-
EXP2_RCLK_DIFF_n10
3.3V
EXP2_DIFF_p8
EXP2_DIFF_n8
3.3V
EXP2_DIFF_p6
EXP2_DIFF_n6
3.3V
EXP2_DIFF_p2
EXP2_DIFF_n2
3.3V
EXP2_DIFF_p0
EXP2_DIFF_n0
EXP2_DIFF_p4
EXP2_DIFF_n4
3.3V
Net Name
www.xilinx.com
EXP Connector
Pin No. (JX1)
100
102
104
112
114
116
118
120
106
108
110
90
92
94
96
98
Spartan-3A DSP Starter Platform User Guide
101
103
113
115
117
119
105
107
109
111
89
91
93
95
97
99
EXP2_DIFF_n11
3.3V
EXP2_DIFF_p9
EXP2_DIFF_n9
3.3V
EXP2_DIFF_p7
EXP2_DIFF_n7
3.3V
EXP2_DIFF_p3
EXP2_DIFF_n3
3.3V
EXP2_DIFF_p1
EXP2_DIFF_n1
EXP2_DIFF_p5
EXP2_DIFF_n5
3.3V
Figure
UG454 (v1.1) January 30, 2009
Net Name
9. A download cable
Pin No.
FPGA
AD7
AD6
AE7
AC6
AE4
AE3
AC8
AB7
AF8
AF4
AF3
-
-
-
-
-
R