AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 57

• Manufacturer Part Number: AT91SAM9M10-G45-EK
• Description: KIT EVAL FOR AT91SAMG45/9M10
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9M10-G45-EK

• Contents: Board, Cables, Power Supply
• Processor To Be Evaluated: AT91SAM9M10
• Processor Series: AT91SAM9
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, JTAG
• Operating Supply Voltage: 5 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Features: Two High Speed USB Hosts, LCD TFT Display
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9M10,
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9M10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D
C
B
A
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
EBI Bus Impedance Adaptor
{3}
EBI0
EBI0_A[0..13]
EBI0_CKE
EBI0_CLK
EBI0_NCLK
EBI0_BA0
EBI0_BA1
EBI0_W E
EBI0_CS
EBI0_RAS
EBI0_CAS
EBI0_DQM0
EBI0_DQM1
EBI0_DQS0
EBI0_DQS1
EBI0_D[0..15]
8
8
EBI0_D10
EBI0_D11
EBI0_D13
EBI0_D14
EBI0_D15
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D12
EBI0_A0
EBI0_A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
R40
R40
R42
R42
R44
R44
R46
R46
R48
R48
4
1
3
2
3
4
1
2
2
4
2
1
3
4
1
3
2
4
4
2
1
3
1
3
1
2
3
3
4
2
1
4
3
2
4
1
2
1
3
4
RR16D
RR16D
RR26A
RR26A
RR16C
RR16C
RR26B
RR26B
RR29C
RR29C
RR29D
RR29D
RR29A
RR29A
RR29B
RR29B
RR4B
RR4B
RR2D
RR2D
RR2B
RR2B
RR4A
RR4A
RR4C
RR4C
RR4D
RR4D
RR2A
RR2A
RR2C
RR2C
RR6B
RR6B
RR8D
RR8D
RR6D
RR6D
RR8B
RR8B
RR8A
RR8A
RR6C
RR6C
RR6A
RR6A
RR8C
RR8C
RR10A
RR10A
RR10B
RR10B
RR10C
RR10C
RR12C
RR12C
RR10D
RR10D
RR12B
RR12B
RR12A
RR12A
RR14D
RR14D
RR14C
RR14C
RR14B
RR14B
RR12D
RR12D
RR14A
RR14A
RR16B
RR16B
RR16A
RR16A
RR26C
RR26C
RR26D
RR26D
27R
27R
27R
27R
27R
27R
27R
27R
27R
27R
5
8
6
7
6
5
8
7
7
5
7
8
6
5
8
6
7
5
5
7
8
6
8
6
7
6
6
5
7
8
5
6
7
5
8
7
8
6
5
8
7
7
DDR_A2
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_CKE {5}
DDR_CLK {5}
DDR_NCLK {5}
DDR_BA0 {5}
DDR_BA1 {5}
DDR_W E {5}
DDR_CS {5}
DDR_RAS {5}
DDR_CAS {5}
DDR_DQM0 {5}
DDR_DQM1 {5}
DDR_DQS0 {5}
DDR_DQS1 {5}
DDR_D[0..15]
DDR_A[0..13]
{3}
{3}
EBI1_D[0..15]
{5}
{5}
EBI1_NCS1/SDCS
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
6
6
EBI1_SDCKE
EBI1_SDCK
EBI1_NSDCK
EBI1_SDW E
EBI1_RAS
EBI1_CAS
EBI1_DQM0
EBI1_DQM1
EBI1_DQS0
EBI1_DQS1
EBI1_SDA10
EBI1_A16
EBI1_A17
EBI1_D11
EBI1_D5
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
SDA10
1
2
1
2
4
3
3
4
1
2
3
4
1
2
3
4
4
3
2
1
3
4
2
1
1
2
3
4
4
3
2
1
RR9A
RR9A
RR9B
RR9B
RR11A
RR11A
RR11B
RR11B
RR11D
RR11D
RR11C
RR11C
RR9C
RR9C
RR9D
RR9D
RR13A
RR13A
RR13B
RR13B
RR13C
RR13C
RR13D
RR13D
RR17A
RR17A
RR17B
RR17B
RR17C
RR17C
RR17D
RR17D
RR19D
RR19D
RR19C
RR19C
RR21B
RR21B
RR21A
RR21A
RR25C
RR25C
RR25D
RR25D
RR23B
RR23B
RR23A
RR23A
RR25A
RR25A
RR25B
RR25B
RR23C
RR23C
RR23D
RR23D
RR21D
RR21D
RR21C
RR21C
RR19B
RR19B
RR19A
RR19A
8
7
8
7
5
6
6
5
8
7
6
5
8
7
6
5
5
6
7
8
6
5
7
8
8
7
6
5
5
6
7
8
R41
R41
R43
R43
R45
R45
R47
R47
R49
R49
1
3
2
1
2
3
4
1
RR31A
RR31A
RR31C
RR31C
RR33B
RR33B
RR33A
RR33A
RR15B
RR15B
RR33C
RR33C
RR33D
RR33D
RR32A
RR32A
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_FLASH_D7
EBI1_FLASH_D11
EBI1_NAND_FSH_D13
5
5
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D6
EBI1_NAND_FSH_D7
EBI1_FLASH_D8
EBI1_NAND_FSH_D8
EBI1_FLASH_D9
EBI1_NAND_FSH_D9
EBI1_FLASH_D10
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_FLASH_D12
EBI1_NAND_FSH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_NAND_FSH_D14
EBI1_FLASH_D15
EBI1_NAND_FSH_D15
27R
27R
27R
27R
27R
27R
27R
27R
27R
27R
8
6
7
8
7
6
5
8
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
EBI1_FLASH_D[0..15]
CKE_EBI1 {6}
CLK_EBI1 {6}
NCLK_EBI1 {6}
BA0_EBI1 {6}
BA1_EBI1 {6}
CS_EBI1 {6}
W E_EBI1 {6}
RAS_EBI1 {6}
CAS_EBI1 {6}
DQM0_EBI1 {6}
DQM1_EBI1 {6}
DQS0_EBI1 {6}
DQS1_EBI1 {6}
4
1
2
3
2
1
4
3
3
1
2
4
1
3
2
4
4
4
RR1D
RR1D
RR1A
RR1A
RR1B
RR1B
RR1C
RR1C
RR3B
RR3B
RR3A
RR3A
RR3D
RR3D
RR3C
RR3C
RR5C
RR5C
RR7A
RR7A
RR5B
RR5B
RR7D
RR7D
RR5A
RR5A
RR7C
RR7C
RR7B
RR7B
RR5D
RR5D
5
8
7
6
7
8
5
6
6
8
7
5
8
6
7
5
EBI1_DDR_D3
EBI1_DDR_D13
{6}
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D14
EBI1_DDR_D15
{3}
EBI1_A[1..18]
{3,6}
{3}
{3}
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
PC2
PC3
PC4
3
3
(A19)
(A20)
(A21)
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_A16
EBI1_A17
EBI1_A18
SDA10
EBI1_DDR_D[0..15]
EBI1_NAND_FSH_D[0..15]
AT91SAM9M10-G45-EK
AT91SAM9M10-G45-EK
AT91SAM9M10-G45-EK
RES.ARRAYS-EBI0_EBI1
RES.ARRAYS-EBI0_EBI1
RES.ARRAYS-EBI0_EBI1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
2
3
4
1
2
3
4
1
2
3
2
1
1
2
1
4
4
1
3
4
1
2
3
4
4
3
3
2
4
3
2
4
1
2
3
4
RR30B
RR30B
RR30C
RR30C
RR18D
RR18D
RR18A
RR18A
RR28B
RR28B
RR28C
RR28C
RR30D
RR30D
RR15A
RR15A
RR18B
RR18B
RR18C
RR18C
RR20B
RR20B
RR20A
RR20A
RR22A
RR22A
RR22B
RR22B
RR30A
RR30A
RR28D
RR28D
RR24D
RR24D
RR28A
RR28A
RR20C
RR20C
RR20D
RR20D
RR27A
RR27A
RR27B
RR27B
RR22C
RR22C
RR22D
RR22D
RR27D
RR27D
RR27C
RR27C
RR15C
RR15C
RR24B
RR24B
RR15D
RR15D
RR24C
RR24C
RR31B
RR31B
RR31D
RR31D
RR24A
RR24A
RR32B
RR32B
RR32C
RR32C
RR32D
RR32D
2
2
{6}
7
6
5
8
7
6
5
8
7
6
7
8
8
7
8
5
5
8
6
5
8
7
6
5
5
6
6
7
5
6
7
5
8
7
6
5
{6}
EBI1_DDR_A12
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
EBI1_FLASH_A1
EBI1_DDR_A2
EBI1_FLASH_A2
EBI1_DDR_A3
EBI1_FLASH_A3
EBI1_DDR_A4
EBI1_FLASH_A4
EBI1_DDR_A5
EBI1_FLASH_A5
EBI1_DDR_A6
EBI1_FLASH_A6
EBI1_DDR_A7
EBI1_FLASH_A7
EBI1_DDR_A8
EBI1_FLASH_A8
EBI1_DDR_A9
EBI1_FLASH_A9
EBI1_DDR_A10
EBI1_FLASH_A10
EBI1_DDR_A11
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_DDR_A13
EBI1_FLASH_A13
EBI1_DDR_A14
EBI1_FLASH_A14
EBI1_DDR_A15
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
REV
REV
REV
SCALE
SCALE
SCALE
A2
A2
A2
A
A
A
MODIF.
MODIF.
MODIF.
1/1
1/1
1/1
(SDA10)
Derek
Derek
Derek
PP
PP
PP
DES.
DES.
DES.
08-apr-10
08-apr-10
08-apr-10
05-Feb-10
05-Feb-10
05-Feb-10
DATE
DATE
DATE
EBI1_FLASH_A[1..21]
EBI1_DDR_A[2..15]
1
EBI1
1
PP
PP
PP
VER.
VER.
VER.
REV.
REV.
REV.
A2
A2
A2
11-FEB-10
11-FEB-10
11-FEB-10
SHEET
SHEET
SHEET
DATE
DATE
DATE
4
4
4
12
12
12
{6}
{6}
D
C
B
A