ADZS-BF518F-EZBRD Analog Devices Inc, ADZS-BF518F-EZBRD Datasheet - Page 40

• Manufacturer Part Number: ADZS-BF518F-EZBRD
• Description: BOARD EVAL BF512F/14F/16F/18F
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADZS-BF518F-EZBRD

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Board, Cables, CD
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: JTAG Emulator Or Standalone Debug Agent Board
• Kit Contents: Board Only
• Silicon Family Name: Blackfin
• Architecture: DSP
• Ide Included: Visual DSP++
• Code Gen Tools Included: Visual DSP++
• Debugger Included: Visual DSP++
• Silicon Core Number: ADSP-BF518F
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: BF512F/14F/16F/18F
• For Use With: ADZS-BFBLUET-EZEXT - EZ-EXTENDER DAUGHTERBOARD
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADSP-BF512/BF514/BF516/BF518(F)
Serial Peripheral Interface (SPI) Port—Master Timing
Table 31
Table 31. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
CPHA=1
CPHA=0
and
(INPUT)
(INPUT)
(OUTPUT)
SPIxSELy
(OUTPUT)
(OUTPUT)
MISOx
MISOx
(CPOL = 0)
(CPOL = 1)
Figure 20
(OUTPUT)
(OUTPUT)
MOSIx
MOSIx
SCKx
SCKx
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISELx low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
VALID
MSB
MSB
t
t
SPICHM
SPICLM
VALID
t
MSB
HSPIDM
Figure 20. Serial Peripheral Interface (SPI) Port—Master Timing
t
t
SPICHM
MSB
SPICLM
Rev. PrE | Page 40 of 62 | March 2009
t
HDSPIDM
t
HDSPIDM
t
DDSPIDM
t
t
SPICLK
t
DDSPIDM
SSPIDM
VALID
LSB
LSB
VALID
LSB
t
HDSM
Preliminary Technical Data
LSB
t
HSPIDM
Min
11.6
–1.5
2 t
2 t
2 t
4 t
2 t
2 t
0
–1.0
t
SPITDM
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
–1.5
–1.5
–1.5
–1.5
Max
6
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns