ADZS-BF518F-EZLITE Analog Devices Inc, ADZS-BF518F-EZLITE Datasheet - Page 44

• Manufacturer Part Number: ADZS-BF518F-EZLITE
• Description: KIT EZ LITE BF512F/14F/16F/18F
• Manufacturer: Analog Devices Inc
• Type: DSPr

Specifications of ADZS-BF518F-EZLITE

• Featured Product: Blackfin® BF50x Series Processors
• Contents: Board, Cables, CD, Head Phones, Power Supply
• Silicon Manufacturer: Analog Devices
• Core Architecture: Blackfin
• Features: USB-based, PC-hosted Tool Set
• Kit Contents: Brd, PSU, CD, Docs, SD Card, Cables
• Silicon Family Name: Blackfin
• Silicon Core Number: ADSP-BF518F
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: BF512F/14F/16F/18F
• For Use With: ADZS-BFBLUET-EZEXT - EZ-EXTENDER DAUGHTERBOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF512/BF514/BF516/BF518(F)
Up/Down Counter/Rotary Encoder Timing
Table 36. Up/Down Counter/Rotary Encoder Timing
1
10/100 Ethernet MAC Controller Timing
Table 37
describe the 10/100 Ethernet MAC Controller operations.
Table 37. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Table 38. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Parameter
t
t
t
t
Parameter
t
t
t
t
Parameter
Timing Requirements
t
t
t
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
MII outputs synchronous to ETxCLK are ETxD3–0.
ERXCLKF
ERXCLKW
ERXCLKIS
ERXCLKIH
ETF
ETXCLKW
ETXCLKOV
ETXCLKOH
WCOUNT
CIS
CIH
through
Up/Down Counter/Rotary Encoder Input Pulse Width
Counter Input Setup Time Before CLKOUT Low
Counter Input Hold Time After CLKOUT Low1
1
1
ERxCLK Frequency (f
ERxCLK Width (t
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
ETxCLK Frequency (f
ETxCLK Width (t
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
CUD/CDG/CZM
Table 42
CLK OUT
and
Figure 26
ETxCLK
ERxCLK
SCLK
SCLK
= ETxCLK Period)
= ERxCLK Period)
= SCLK Frequency)
= SCLK Frequency)
through
Figure 25. Up/Down Counter/Rotary Encoder Timing
Figure 31
Rev. PrE | Page 44 of 62 | March 2009
t
CIS
1
t
WCOUNT
t
CIH
Min
None
t
7.5
7.5
Min
None
t
0
ERxCLK
ETxCLK
Min
t
4.0
4.0
SCLK
Preliminary Technical Data
x 35%
x 35%
V
+ 1
DDEXT
= 1.8 V
Max
Max
25 MHz + 1%
f
t
Max
25 MHz + 1%
f
t
20
SCLK
ERxCLK
SCLK
ETxCLK
+ 1%
+ 1%
4.0
Min
t
4.0
x 65%
x 65%
SCLK
V
DDEXT
+ 1
= 2.5/3.3 V
Max
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns