ADZS-21469-EZLITE Analog Devices Inc, ADZS-21469-EZLITE Datasheet - Page 12

• Manufacturer Part Number: ADZS-21469-EZLITE
• Description: KIT EVAL EZ LITE ADSP-21469
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: DSPr

Specifications of ADZS-21469-EZLITE

• Contents: Board, Cables, Debugger, Power Supply, Software
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Evaluation Version Of VisualDSP++, Debug Agent Board
• Kit Contents: Board Cables CD Docs
• Silicon Family Name: SHARC
• Architecture: DSP
• Ide Included: Visual DSP++
• Code Gen Tools Included: Visual DSP++
• Debugger Included: Visual DSP++
• Silicon Core Number: ADSP-21469
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-2146x
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
Note that the analog supply pin (V
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
V
the V
recommended ferrite chip is the muRata BLM18AG102SN1D).
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
to connect the bypass capacitors to the analog power (V
and ground (V
specified in
log ground plane on the board—the V
directly to digital ground (V
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-2146x pro-
cessors to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor's JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-2146x processors are supported with a complete set
of CROSSCORE
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-2146x processors.
EZ-KIT Lite Evaluation Board
For evaluation of the processors, use the EZ-KIT Lite
being developed by Analog Devices. The board comes with on-
chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
DD_A
V DDINT
DD_A
pin. Place the filter components as close as possible to
/V
Figure 2
HI Z FERRITE
BEAD CHIP
SS_A
Figure 2. Analog Power (V
SS_A
®
pins. For an example circuit, see
software and hardware development tools,
) pins. Note that the V
are inputs to the processor and not the ana-
CLOSE TO V DD_A AND V SS_A PINS
100nF
LOCATE ALL COMPONENTS
SS
) at the chip
DD_INT
10nF
DD_A
DD_A
SS_A
and V
) Filter Circuit
) powers the processor’s
DD_A
pin should connect
1nF
SS
. Use wide traces
and V
Rev. PrC | Page 12 of 62 | January 2009
Figure
SS_A
®
ADSP-2146x
V DD_A
V SS_A
board
®
DD_A
devel-
2. (A
pins
)
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-
circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com-
mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standal-
one unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, non-
intrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-2146x
architecture and functionality. For detailed information on the
ADSP-2146x family core architecture and instruction set, refer
to the ADSP-2136x/ADSP-2146x SHARC Processor Program-
ming Reference.
®
Preliminary Technical Data
development and debugging environment
®
evaluation plat-