ADZS-21469-EZLITE Analog Devices Inc, ADZS-21469-EZLITE Datasheet - Page 33

• Manufacturer Part Number: ADZS-21469-EZLITE
• Description: KIT EVAL EZ LITE ADSP-21469
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: DSPr

Specifications of ADZS-21469-EZLITE

• Contents: Board, Cables, Debugger, Power Supply, Software
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Evaluation Version Of VisualDSP++, Debug Agent Board
• Kit Contents: Board Cables CD Docs
• Silicon Family Name: SHARC
• Architecture: DSP
• Ide Included: Visual DSP++
• Code Gen Tools Included: Visual DSP++
• Debugger Included: Visual DSP++
• Silicon Core Number: ADSP-21469
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-2146x
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Preliminary Technical Data
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK, (setup skew = t
TWH
that can be introduced in LCLK relative to LDATA, (hold skew
= t
Table 29. Link Ports – Receive
1
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
LACK goes low with tDLALC relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLALC
LCLKTWL
min– t
DLDCH
min – t
LDAT7-0
LACK (OUT)
LCLK
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period
LCLK Width Low
LCLK Width High
LACK Low Delay After LCLK High
– t
HLDCH
SLDCL
– t
). Hold skew is the maximum delay
HLDCL
). Calculations made directly
t
LCLKRWH
1
Rev. PrC | Page 33 of 62 | January 2009
t
Figure 20. Link Ports—Receive
SLDCL
IN
LCLK-
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
t
LCLKIW
t
HLDCL
from speed specifications will result in unrealistically small skew
times because they include multiple tester guardbands. The
setup and hold skew times shown below are calculated to
include only one tester guardband.
Setup Skew = TBD ns max
Hold Skew = TBD ns max
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
t
LCLKRWL
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
DLALC
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns