ADZS-21469-EZLITE Analog Devices Inc, ADZS-21469-EZLITE Datasheet - Page 21

• Manufacturer Part Number: ADZS-21469-EZLITE
• Description: KIT EVAL EZ LITE ADSP-21469
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: DSPr

Specifications of ADZS-21469-EZLITE

• Contents: Board, Cables, Debugger, Power Supply, Software
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Evaluation Version Of VisualDSP++, Debug Agent Board
• Kit Contents: Board Cables CD Docs
• Silicon Family Name: SHARC
• Architecture: DSP
• Ide Included: Visual DSP++
• Code Gen Tools Included: Visual DSP++
• Debugger Included: Visual DSP++
• Silicon Core Number: ADSP-21469
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-2146x
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Preliminary Technical Data
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 41 on Page 52
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
RESET
XTAL
BUF
CLKIN
4096 CLKIN
DELAY OF
CYCLES
under Test Conditions for voltage refer-
DIVIDER
CLKIN
PMCTL
PLLI
RESETOUT
CLK
Figure 3. Core Clock and System Clock Relationship to CLKIN
CLK_CFGx/PMCTL
FILTER
LOOP
MULTIPLIER
Rev. PrC | Page 21 of 62 | January 2009
CLKOUT
PLL
PLL
VCO
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
DIVIDER
PLL
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
CLK_CFGx/
PMCTL
PMCTL
CCLK
BUF
DIVIDER
MLB CLOCK
PMCTL
DIVIDE
LINKPORT
DDR2
BY 2
PMCTL
DIVIDER
DIVIDER
CLOCK
PMCTL
PCLK
RESETOUT/
CORERST
CLKOUT
CLK_CFGx/
PMCTL
CLK_CFGx/
CLK_CFGx/
PMCTL
PMCTL
PCLK
CCLK
MLBSYSCLK
DDR2_CLK
LCLK