DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 66

KIT DEV ARRIA II GX FPGA 2AGX125

DK-DEV-2AGX125N

Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr

Specifications of DK-DEV-2AGX125N

Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-DEV-2AGX125N
Manufacturer:
ALTERA
0
1–58
Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
f
f
f
f
f
t
IN
INPFD
VCO
INDUTY
EINDUTY
INCCJ
(4)
Symbol
(3),
Core Performance Specifications for the Arria II Device Family
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–4 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–5 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–6 Speed Grade)
Input frequency to the PFD
PLL VCO operating Range
Input clock duty cycle
External feedback clock input duty cycle
Input clock cycle-to-cycle jitter (Frequency  100 MHz)
Input clock cycle-to-cycle jitter (Frequency  100 MHz)
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), embedded memory, configuration, and JTAG specifications for
Arria II GX and GZ devices.
Clock Tree Specifications
Table 1–42
Table 1–42. Clock Tree Performance for Arria II GX Devices
Table 1–43
Table 1–43. Clock Tree Performance for Arria II GZ Devices
PLL Specifications
Table 1–44
GCLK and RCLK
GCLK and RCLK
Clock Network
Clock Network
PCLK
PCLK
lists the clock tree specifications for Arria II GX devices.
lists the clock tree specifications for Arria II GZ devices.
lists the PLL specifications for Arria II GX devices.
Description
(2)
I3, C4
500
420
–C3 and –I3
700
500
Performance
Performance
C5,I5
500
350
Min
600
40
40
Chapter 1: Device Datasheet for Arria II Devices
5
5
5
5
–C4 and –I4
Typ
500
450
December 2010 Altera Corporation
400
280
C6
670
622
500
1,400
±750
Max
0.15
325
60
60
Switching Characteristics
(1)
(1)
(1)
ps (p–p)
UI (p–p)
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
Unit
%
%

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