DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 73

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2010 Altera Corporation
Configuration
Table 1–50
Table 1–50. Configuration Mode Specifications for Arria II Devices
JTAG Specifications
Table 1–51
devices.
Table 1–51. JTAG Timing Parameters and Values for Arria II Devices
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–52
and GZ devices.
Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices
Passive serial
Fast passive parallel
Fast active serial (fast clock)
Fast active serial (slow clock)
Remote update only in fast AS mode
t
t
t
t
t
t
t
t
t
Dev_CLRn
JCP
JCH
JCL
JPSU (TDI)
JPSU (TMS)
JPH
JPCO
JPZX
JPXZ
Symbol
lists the configuration mode specifications for Arria II GX and GZ devices.
lists the JTAG timing parameters and values for Arria II GX and GZ
lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX
TCK clock period
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Programming Mode
Description
Description
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
8.5
—
—
17
—
Min
500
DCLK Frequency
Min
30
14
14
—
—
—
1
3
5
Typ
—
—
26
13
—
Typ
—
Max
—
—
—
—
—
—
11
14
14
Max
125
125
40
20
10
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Unit
Unit
s
1–65