DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 27

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Chapter 6: Board Test System
Using the Board Test System
The DDR2 Tab
© October 2009 Altera Corporation
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If you enter an address outside of the 0x0000.0000 to 0x001F.FFFF SRAM address
space, a warning message identifies the valid SRAM address range.
To update the SRAM contents, change values in the table and click Write. The
application writes the new values to SRAM and then reads the values back to
guarantee that the graphical display accurately reflects the memory contents.
Flash
This control allows you to read and write the flash memory on your board. Type a
starting address in the text box and click Read. Values starting at the specified address
appear in the table.The base address of flash memory in this Nios II-based BTS design
is 0x0800.0000. The valid address range within the 64-MByte SRAM is 0x0000.0000
through 0x03FF.FFFF, as shown in the GUI.
If you enter an address outside of the 0x0000.0000 to 0x003F.FFFF flash memory
address space, a warning message identifies the valid flash memory address range.
To update the flash memory contents, change values in the table and click Write. The
application writes the new values to flash memory and then reads the values back to
guarantee that the graphical display accurately reflects the memory contents.
To prevent overwriting the dedicated portions of flash memory, the application limits
the writable flash memory address range to 0x03FE.0000 to 0x003F.FFFF (which
corresponds to the unused flash memory address range shown in
page 6–2
The DDR2 tab allows you to read and write the DDR2 memory on your board.
Figure 6–5
and
shows the DDR2 tab.
Table A–1 on page
A–1).
Cyclone III LS FPGA Development Kit User Guide
Figure 6–1 on
6–9