DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 28

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

6–10
Figure 6–5. The DDR2 Tab
Cyclone III LS FPGA Development Kit User Guide
The following sections describe the controls on the DDR2 tab.
Port
This control directs communication to one of two DDR2 memory ports on your board.
Start
This control initiates DDR2 port transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:

Write, Read, and Total performance bars—Show the percentage of maximum data
rate that the requested transactions are able to achieve.
© October 2009 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System