DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 31

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Chapter 6: Board Test System
The Power Monitor
The Power Monitor
© October 2009 Altera Corporation
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Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
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Error Control
These controls track transaction errors detected during analysis.
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Start
This control initiates HSMC transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
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The Power Monitor measures and reports current power information for the board. To
start the application, click Power Monitor in the Board Test System application.
HSMA x41 Single Ended Loopback
HSMB x41 Single Ended Loopback
PRBS—Selects pseudo-random bit sequences.
Memory—Selects a generic data pattern stored in the on chip memory of the
Cyclone III LS device. This feature is not currently implemented.
Math—Selects data generated from a simple math function within the FPGA
fabric. This feature is not currently implemented.
Detected Errors—Displays the number of transaction errors detected in the
hardware.
Inserted Errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected Errors and Inserted Errors counters to zeros.
TX and RX performance bars—Show the percentage of maximum data rate that
the requested transactions are able to achieve.
Tx(MBytes/s) and Rx(MBytes/s)—Show the number of bytes of data analyzed per
second.
Cyclone III LS FPGA Development Kit User Guide
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