DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 29

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Chapter 6: Board Test System
Using the Board Test System
The HSMC Tab
© October 2009 Altera Corporation
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Error Control
These controls track transaction errors detected during analysis:
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Number of addresses to write / read
This control determines the number of addresses to use in each iteration of reads and
writes. Valid values range from 2 to 8,191.
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
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Read/Write control
This control specifies the type of transactions to analyze. The following transaction
types are available for analysis:
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The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B
ports.
Write(MBytes/s), Read(MBytes/s), and Total(MBytes/s)—Show the number of
bytes of data analyzed per second. Each data bus is 16 bits wide and the frequency
is 167 MHz double data rate (334 Mbps per pin), equating to a theoretical
maximum bandwidth of 668 MBps.
Detected Errors—Displays the number of transaction errors detected in the
hardware.
Inserted Errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected Errors and Inserted Errors counters to zeros.
PRBS—Selects pseudo-random bit sequences.
Memory—Selects a generic data pattern stored in the on chip memory of the
Cyclone III LS device.
Math—Selects data generated from a simple math function within the FPGA
fabric.
Write/Read—Selects read and write transactions for analysis.
Read Only—Selects read transactions for analysis.
Write Only—Selects write transactions for analysis.
Figure 6–6
shows the HSMC tab.
Cyclone III LS FPGA Development Kit User Guide
6–11