EDOSK2674 Renesas Electronics America, EDOSK2674 Datasheet - Page 26

• Manufacturer Part Number: EDOSK2674
• Description: DEV EVALUATION KIT H8S/2674
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of EDOSK2674

• Contents: EDOSK (Evaluation Development Operating System Kit) Board
• For Use With/related Products: H8S/2674R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SDRAM Notes:
Prior to using the SDRAM the mode must be set in the SMR (SDRAM Mode Register).
The SMR should be set to the value B’0000 0010 0000 – CAS latency 2, Burst 1. This is achieved by a write cycle to
the SDRAM at an address equal to the required SMR value when in configuration mode.
The address to set the SMR should be H’400040 – SDRAM starts at area H’400000 and the SMR value must be
shifted to compensate for word access.
Example:
DRAM Access Control Register:
DRACCR (H’FFFED2) = H’0000
Bit No
Bit Name
Initial Value
Bit No
Bit Name
Initial Value
Idle cycle not inserted, 1-State Pre-charge, CAS latency enabled, No wait between RAS and CAS cycles.
No clock suspend, 1-State read data extension cycle.
Refresh Control Register:
REFCR (H’FFFED4) = H’0188
Bit No
Bit Name
Initial Value
Bit No
Bit Name
Initial Value
No wait states between CAS and RAS, REF count on /2
Enable refresh control, No waits for
precharge cycle immediately after self refreshing.
1.
2.
3.
4.
Configure all other SDRAM Registers.
DRAMCR = 0x85B4; //SMR configuration mode
SDRAM_CONTROL = 0; // where SDRAM_CONTROL is H’400040
DRAMCR = 0x84B4; //Return to SDRAM operating mode
15
DRMI
0
7
Reserved
0
15
CMF
0
7
RFSHE
1
14
Reserved
0
6
Reserved
0
14
CMIE
0
6
CBRM
0
CAS-before-RAS refresh cycle, Self refresh enabled, zero states in the
13
TPC1
0
5
Reserved
0
13
RCW1
0
5
RLW1
0
12
TPC0
0
4
Reserved
0
12
RCW0
0
4
RLW0
0
11
SDWCD
0
3
CKSPE
0
11
Reserved
0
3
SLFRF
1
10
Reserved
0
2
Reserved
0
10
RTCK2
0
2
TPCS2
0
9
RCD1
0
1
RDXC1
0
9
RTCK1
0
1
TPCS1
0
8
RCD0
0
0
RDXC0
0
8
RTCK0
1
0
TPCS0
0
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