EDOSK2674 Renesas Electronics America, EDOSK2674 Datasheet - Page 9

• Manufacturer Part Number: EDOSK2674
• Description: DEV EVALUATION KIT H8S/2674
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of EDOSK2674

• Contents: EDOSK (Evaluation Development Operating System Kit) Board
• For Use With/related Products: H8S/2674R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.5. MAIN F
The MAIN Flash memory is a 4MByte device (INTEL 28F320J3A) and is word accessed.
The MCU interfaces with the MAIN Flash on reset in area 0 only when the EDOSK is set to Normal mode.
In Normal mode the MAIN Flash is designed to reside in area 0 and area 1.
In Boot mode the MAIN Flash is designed to reside in area 1 only and is paged by driving port pin 33.
The Main Flash may be programmed in system when write enable jumper is fitted.
Details of BSC register settings for the Intel Flash memory can be found in section 7.2.
Main Flash access:
2.6. RAM
The H8/2674R has 32KB of RAM available on-chip. This RAM can be enabled or disabled by means of the RAME bit in the
system control register (SYSCR). Initially this RAM is enabled.
2.7. SDRAM
The H8/2674R, external address space areas 2 to 5, has been designated as continuous Synchronous DRAM space. An
8MB external SDRAM interfaces directly to the MCU.
The SDRAM used is a MICRON MT48LC4M16A2:
Row addressing: 4K (A0-A11)
Bank addressing: 4 (BA0, BA1)
Column addressing: 512 (A0-A8)
MCU port pin 34 is used to drive the SDRAM CS pin.
Details of BSC and DRAM register settings for the SDRAM can be found in section 7.2.
SDRAM access:
2.8. LAN C
The LAN controller IC is a SMSC LAN91C96 device. The base address of this device defaults to 300h, however the EDOSK
re-maps this to F80000h.
The MAC address is contained within a removable EEPROM connected to the Controller. This is programmed during
production testing and should not be altered.
Details of BSC register settings for the LAN controller can be found in section 7.2.
LAN Controller access:
Extended CS period: T
Bus Width: 16 bit.
Access States: 3
Wait States: 2
Cycle burst: 6
Bus Width: 16 bit.
Bus Width: 8 bit.
Access States: 3
Wait States: 3
Extended CS period: T
ONTROLLER
LASH
M
EMORY
h
h
and T
and T
t
t
(area 7 only)
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