EDOSK2674 Renesas Electronics America, EDOSK2674 Datasheet - Page 29

• Manufacturer Part Number: EDOSK2674
• Description: DEV EVALUATION KIT H8S/2674
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of EDOSK2674

• Contents: EDOSK (Evaluation Development Operating System Kit) Board
• For Use With/related Products: H8S/2674R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.2.4. W
Timer Control/Status Register:
TCSR (H’FFFFBC) = H’18
Bit No
Bit Name
Initial Value
Timer Counter:
TCNT (H’FFFFBC-write / H’FFFFBD-read) = H’00
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0.
Reset Control/Status Register:
RSTCSR (H’FFFFBE) = H’1F
Bit No
Bit Name
Initial Value
To prevent accidental overwriting, access of WDT registers is different from other registers.
The WDT may be used to drive the ‘TIMER’ LED when the counter overflows. This, however, is a very short period
and in order to see the LED with the naked eye the WDT must be forced to overflow repeatedly.
Example to keep LED on:
7.2.5. IO P
Port Function Control Register 0:
PFCR0 (H’FFFE32) = H’FF
Bit No
Bit Name
Initial Value
Enable all CS signals
TCSR = 0xA500; // clear lower byte.
TCSR = 0xA578; // setup & Enable the watchdog timer.
while( 1)
{
}
ATCHDOG
7
OVF
0
7
WOVF
0
7
CS7E
1
ORT
if( RSTCSR & 0x0080 ) // detect overflow and reset WDT.
{
}
T
IMER
WT/IT
6
0
6
RSTE
0
6
CS6E
1
RSTCSR = 0xA500; // clear watchdog overflow bit.
TCSR = 0xA578;
5
TME
0
5
Reserved
0
5
CS5E
1
// clear overflow bit and enable WDT.
4
Reserved
1
4
Reserved
1
4
CS4E
1
3
Reserved
1
3
Reserved
1
3
CS3E
1
2
CKS2
0
2
Reserved
1
2
CS2E
1
CKS1
1
0
1
Reserved
1
1
CS1E
1
0
CKS0
0
0
Reserved
1
0
CS0E
1
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