MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 107

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
TSEC3_TX_CLK/FEC_TX_CL
K/FIFO3_TX_CLK
TSEC3_TX_EN/FEC_TX_EN/F
IFO3_TX_EN
TSEC4_TXD[3:0]/TSEC3_TXD[
7:4]/FIFO3_TXD[7:4]
TSEC4_RXD[3:0]/TSEC3_RXD
[7:4]/FIFO3_RXD[7:4]
TSEC4_GTX_CLK
TSEC4_RX_CLK/TSEC3_COL/
FEC_COL/FIFO3_TX_FC
TSEC4_RX_DV/TSEC3_CRS/
FEC_CRS/FIFO3_RX_FC
TSEC4_TX_EN/TSEC3_TX_E
R/FEC_TX_ER/FIFO3_TX_ER
UART_CTS[0:1]
UART_RTS[0:1]
UART_SIN[0:1]
UART_SOUT[0:1]
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
SD1_RX[7:0]
SD1_RX[7:0]
SD1_TX[7]
Signal
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Transmit Clock In
Transmit Enable
Transmit Data
Receive Data
Transmit Clock Out
Receive Clock
Receive Data Valid
Transmit Enable
Clear to Send
Ready to Send
Receive Data
Transmit Data
Serial Clock
Serial Data
Serial Clock
Serial Data
Receive Data (positive)
Receive Data (negative)
PCIe1 Tx Data Lane 7 / SRIO or
PCIe2 Tx Data Lane 3 / PCIe3
TX Data Lane 1
Table 76. MPC8572E Pinout Listing (continued)
Signal Name
Three-Speed Ethernet Controller 4
SerDes (x10) PCIe, SRIO
I
2
C Interface
DUART
AF16
AB15
AJ18
AD15, AC16, AC14,
AB16
AE15, AF13, AE14,
AH14
AB14
AG13
AD13
W30, Y27
W31, Y30
Y26, W29
Y25, W26
AC30
AB30
AD30
AD29
P32, N30, M32, L30,
G30, F32, E30, D32
P31, N29, M31, L29,
G29, F31, E29, D31
M26
Package Pin Number
Pin Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
XV
XV
XV
Supply
Power
Package Description
TV
TV
TV
TV
TV
TV
TV
TV
OV
OV
OV
OV
OV
OV
OV
OV
DS1
DS1
DS1
DD_SR
DD_SR
DD_SR
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Notes
1, 5, 9
1, 22
1, 23
1, 22
4, 20
4, 20
4, 20
4, 20
5, 9
5, 9
—
—
—
—
—
—
1
1
1
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