DO-CPLD-DK-J-G Xilinx Inc, DO-CPLD-DK-J-G Datasheet
DO-CPLD-DK-J-G
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CPLD I/O User Guide UG445 (v1.1) November 27, 2007 R ...
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... Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. ...
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... Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CPLD I/O User Guide Terminations ...
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UG445 (v1.1) November 27, 2007 R CPLD I/O User Guide ...
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... I/Os. It includes details on how much voltage can be driven into a Xilinx CPLD and the behavior of the I/Os in different operating conditions. Additional Resources To find additional documentation, see the Xilinx Web site at: http://www.xilinx.com/support/documentation/index.htm. To search the Answer Database of silicon, software, and IP questions and answers create a technical support WebCase, see the Xilinx Support Web site at: http://www ...
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... This application note describes the features and benefits of the I/O cells provided by Xilinx CoolRunner XPLA3 CPLDs. • XAPP382 This document is a comprehensive description of the I/O structure of the CoolRunner-II CPLD family. • XAPP429 This application note describes several different methods for interfacing 5V signals to CoolRunner-II devices ...
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... R Online Document The following conventions are used in this document: Convention Blue text Blue, underlined text CPLD I/O User Guide UG445 (v1.1) November 27, 2007 Meaning or Use See the section Resources” Cross-reference link to a location in the current In the example in document the Volmax is 0.5V, you can sink 21 mA ...
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Preface: About This Guide 8 www.xilinx.com UG445 (v1.1) November 27, 2007 R CPLD I/O User Guide ...
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R CPLD I/O User Guide Terminations Terminations are a vital aspect of a robust transmission line. The on-chip termination of the CPLD I/Os eliminate the need for external termination strongly recommended not to float CMOS inputs as this ...
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... Right-click and select Properties. The Fit Properties dialog box appears. There is a drop-down menu for the Input and Tristate I/O termination mode. For the CoolRunner-II and CoolRunner XPLA3, there is a drop-down menu for the Unused I/O Pad termination. However, if the design targets an XC9500, XC9500XL, or XC9500XV, there are only two options for the unused termination ...
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... The trip-point for the newer devices (part marking of *MN) is lower than the trip-point for the older devices (part marking of APN); this can result in the half latch circuitry being “turned on” sooner than in the older devices. If this occurs, a pull-down resistor of a value stronger than 10K is required to overcome the half latch pull-up resistance; a value of 4.7k CPLD I/O User Guide UG445 (v1 ...
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... The XC9500 families do not have a half latch. The XC9500XL and XC9500XV have internal circuitries that function in a similar manner to a half latch. To overcome this circuitry, ensure that a pull-down of 4K7 ohm or stronger is used. (The effective resistance of the internal circuitry is between 30k - 60k Ohm.) ...
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... I/O). The threshold that the CPLD drives out can be determined by the Vihmin of the downstream device (i.e., if the downstream device requires a Vihmin of 3.0V, then you must ensure that the CPLD can drive out this voltage with its current loading) ...
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Thresholds If you want to find out how much current an I/O can sink before you raise the voltage level above Volmax, you can look at the Iol (output low current) curve in and trace to the corresponding current value. ...
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... From the curve (see will be 2.8V, which is above the Vohmin requirement for both the LVCMOS33 and LVTTL standards. The user must ensure that the Vohmin requirement meets the Vihmin of the downstream device. Maximum I/O Power Dissipation As an example, you might want to know how to calculate the maximum number of I/Os one device can sink or source before damaging the device ...
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... You will need to expand Pd to take into account Pd of the design and the I/O: (Pddesign + PdIO) = 1.613W Pddesign from measurement; doubled to 132 mW for safety cushion. When sourcing 40 mA, the voltage at the output of the CPLD will be 2.3V (information obtained from the I/V curve). ...
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... The maximum voltage that you can you drive into an I/O with the device powered or unpowered, is limited to the Vi/Vin parameter in the family data sheet. • XC9500: You can drive into an unpowered I/O, provided Vin does not exceed the Vin limits of the CPLD. • ...
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... CCIO begins rising (i.e., scenario 1 and 2), the I/Os will track V the I/Os is active. This may be seen as Logic High to a downstream device. If the output should be driving low at power-up, then the tracking of the I glitch. However, this is the intended behavior as specified in the data sheet. An example ...
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R For best results (with multiple power rails), Xilinx recommends that V before V CCIO are active might be glitches on the I/O as the internal circuitry is initialized. Xilinx recommends not leaving V CCIO During power-up, all ...
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Power, Sequencing, and Slew Rates on V CCAUX TAP controller cannot be guaranteed. Current Consumption Programming is defined as the process of programming the non-volatile memory. Configuration is defined as the process of the CPLD self-configuring upon power-up (Tconfig). Programming ...
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... CoolRunner-II devices are not 5V-tolerant. For other CPLDs, the basic strategy is to configure the I/O structure so that it drives either high-Z. Then, use an external pull-up resistor (.5K to 1K this, run the output signal logic to the enable of the OBUFT. The logic input of the OBUFT is connected to ground ...
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... Schmitt Trigger CoolRunner-II is the only family to have the Schmitt trigger feature. A Schmitt trigger is an input circuit used to reduce noise on the input signal. In CoolRunner-II devices, there is a Schmitt trigger available on all I/Os, but only with the I/O standards that do not require a VREF. 22 data_to_pin : inout std_logic) ...
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R In Figure 8 noise from the outputs that make the non-Schmitt Trigger input appear jagged. Non-Schmitt Waveforms Figure 8: Before and After Schmitt Trigger Waveforms When the input is higher than a certain chosen threshold, the output is high; ...
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Power, Sequencing, and Slew Rates 24 Figure 9: Slew Rate www.xilinx.com UG445 (v1.1) November 27, 2007 R UG445_08_052207 CPLD I/O User Guide ...