DO-CPLD-DK-J-G Xilinx Inc, DO-CPLD-DK-J-G Datasheet - Page 11

• Manufacturer Part Number: DO-CPLD-DK-J-G
• Description: KIT STARTER CPLD JAPANESE
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLD Development Kitr

Specifications of DO-CPLD-DK-J-G

• Contents: Proto Board, Download Cable, Software and Documentation
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CPLD I/O User Guide
UG445 (v1.1) November 27, 2007
Impedance of the Bus-hold, Keeper, or Pull-up
Half Latch
R
CoolRunner XPLA3
Programming (ISP) mode, the bus-hold is not active. If the device loses V
will be in a pull-up state. The Bus-hold is enabled by Vccint, but pulls to Vccio.
The values given in this section are typical numbers that cannot be guaranteed as the
impedance varies over process, voltage, and temperature.
CoolRunner-II
The effective resistance of the termination circuitry varies with V
At V
As V
The minimum resistance value presented by the termination circuitry is 20k Ohm.
CoolRunner XPLA3
The CoolRunner does not have a bus-hold. It does have an internal pull-up that has been
characterized at approximately 60k to 150k Ohms.
XC9500, XC9500XL, and XC9500XV
The bus hold impedance is approximately 25k Ohm, with a range of 15K to 70K (the lower
range at lower temperatures).
The CoolRunner XPLA3 has a half latch feature on the I/Os. The half latch is essentially a
pull-up that turns on only when the I/O pin voltage is in the linear region (not a 0, not a 1).
So, when the voltage at the pin is in the trip-point region or higher, the half latch will be
enabled. The idea is that it will prevent signals from floating, and therefore, save power.
This half latch cannot be disabled.
The device data sheet states the following: “The I/O is configured as an input (or 3-stated
output), a half latch feature exists. This half latch pulls the input high (through a weak
pull-up) if the input should float and cross the threshold.”
This means that the half latch feature exists even when the pull-up is not selected. If you
want to pull down the input, a resistor strong enough to overcome the half latch must be
used. Xilinx recommends that any pull-down resistor value be 10k Ohms or less. Xilinx
does not recommend using CoolRunner XPLA3 devices in any design that requires I/O
pins to truly float.
Some CoolRunner XPLA3 devices appear to have a pull-up on the I/O pins when there is
no pull-up specified, this is due to the CoolRunner XPLA3 half latch circuitry. The range of
the trip-point is from 0.9V to 1.6V. There was a change in the trip-point when Xilinx
changed fabs. The change in fab locations is documented in PCNs, and is available on the
Xilinx Customer Notices page:
http://www.xilinx.com/support/documentation/customer_notices.htm.
The trip-point for the newer devices (part marking of *MN) is lower than the trip-point for
the older devices (part marking of APN); this can result in the half latch circuitry being
“turned on” sooner than in the older devices. If this occurs, a pull-down resistor of a value
stronger than 10K is required to overcome the half latch pull-up resistance; a value of 4.7k
CCIO
CCIO
= 1.8V, the effective resistance is typically 100k Ohm.
increases, the effective resistance decreases. Typical for V
www.xilinx.com
CCIO
CCIO
.
=3.3V is 42k Ohm.
CCINT
Terminations
, the I/Os
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