DO-CPLD-DK-J-G Xilinx Inc, DO-CPLD-DK-J-G Datasheet - Page 12

• Manufacturer Part Number: DO-CPLD-DK-J-G
• Description: KIT STARTER CPLD JAPANESE
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLD Development Kitr

Specifications of DO-CPLD-DK-J-G

• Contents: Proto Board, Download Cable, Software and Documentation
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thresholds
Thresholds
12
I/V Curves
CoolRunner-II
XC9500, XC9500XL, and XC9500XV
JTAG Termination
ohm is recommended. If the incorrect value of a pull-down is used, a voltage divider will
be created at the input.
More information on the half latch is available in the XPLA3 I/O Cell Characteristics
Application Note (XAPP342).
The CoolRunner-II I/Os have a half latch feature enabled by default. Half latch occurs only
in cases when the CoolRunner-II I/Os are configured as LVCMOS18 and the Schmitt
trigger is disabled. If the Schmitt trigger is used, the half latch is disabled. When using
LVCMOS18, the only way to turn the half latch off is to enable the Schmitt trigger on that
input.
The XC9500 families do not have a half latch.
The XC9500XL and XC9500XV have internal circuitries that function in a similar manner to
a half latch. To overcome this circuitry, ensure that a pull-down of 4K7 ohm or stronger is
used. (The effective resistance of the internal circuitry is between 30k - 60k Ohm.)
XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI
and TMS.
CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK.
It is not necessary to externally terminate JTAG pins with internal termination; they can be
left floating. External pull-ups on pins with internal termination is allowed, but not
necessary. External pull-down termination is not recommended as it would conflict with
the internal pull-ups.
The I/V curve is a graphical representation of the nominal amount of current that an I/O
can source or sink at different voltage levels. The range of voltage levels, and therefore, the
current, is dependent on the I/O voltage used. The I/V curves provide details on
thresholds.
The I/V curves for the CoolRunner-II and CoolRunner XPLA3 devices can be found in the
family data sheets and in the I/V Curves for Xilinx FPGA and CPLD Families Application Note
(XAPP150) for the XC9500, XC9500XL and XC9500XV families.
Questions often asked by users are:
•
•
How much current can an I/O source or sink?
If I am driving a certain load, what voltage levels can I expect?
www.xilinx.com
UG445 (v1.1) November 27, 2007
CPLD I/O User Guide
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