DO-CPLD-DK-J-G Xilinx Inc, DO-CPLD-DK-J-G Datasheet - Page 18

• Manufacturer Part Number: DO-CPLD-DK-J-G
• Description: KIT STARTER CPLD JAPANESE
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLD Development Kitr

Specifications of DO-CPLD-DK-J-G

• Contents: Proto Board, Download Cable, Software and Documentation
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power, Sequencing, and Slew Rates
18
There are three basic scenarios:
•
•
•
During configuration, the I/Os are placed in a Tristate condition with a weak pull-up to
V
begins rising (i.e., scenario 1 and 2), the I/Os will track V
the I/Os is active. This may be seen as Logic High to a downstream device. If the output
should be driving low at power-up, then the tracking of the I/O to V
a glitch. However, this is the intended behavior as specified in the data sheet. An example
of the tracking of V
CCIO
V
V
V
CCINT
CCIO
CCINT
. If V
before V
CCIO
and V
before V
voltage is either rising with V
CCIO
CCIO
CCINT
CCIO
rise together (both tied to the same 1.8V rail)
Figure 4: V
by the output is shown in
(I/O comes alive before logic)
(logic comes alive before I/O)
www.xilinx.com
CCINT
is powered after V
CCINT
Figure
or is well established before V
CCIO
4.
UG445 (v1.1) November 27, 2007
CCIO
before the logic that drives
CCIO
CPLD I/O User Guide
UG445_03_111607
might appear as
CCINT
R