M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 142

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 118 of 587
Figure 11.7
11.6.4
Table 11.5
NOTE:
Peripheral function
INT instruction
NMI
Watchdog timer
Undefined instruction
Address match
Overflow
BRK instruction (relocatable vector table)
BRK instruction (fixed vector table)
High-speed interrupt
1. The values when interrupt vectors are allocated in even addresses in the internal ROM, except for the high-
Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt request
generation and the end of an interrupt sequence. Interrupt response time is divided into two phases: the period
between an interrupt request generation and the end of the ongoing instruction execution ((a) in Figure 11.7),
and the period required to perform the interrupt sequence ((b) in Figure 11.7).
Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require the
longest time (a), which is at the maximum of 42 cycles.
Table 11.5 lists time (b).
speed interrupt.
Interrupt request is
generated
Interrupt Response Time
(a) Period between an interrupt request generation and the end of instruction execution.
(b) Period required to perform an interrupt sequence.
Interrupt Response Time
Interrupt Sequence Execution Time
Interrupts
Instruction
(a)
Interrupt response time
Interrupt request is
acknowledged
Interrupt sequence
(in terms of CPU clock)
Execution Time
(b)
14 cycles
12 cycles
13 cycles
14 cycles
17 cycles
19 cycles
5 cycles
(1)
Instruction in interrupt routine
Time
11. Interrupts