M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 445

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 421 of 587
Figure 23.15
23.1.12 CANi Slot Interrupt Mask Register (CiSIMKR Register) (i = 0, 1)
CANi Slot Interrupt Mask Register (i = 0, 1)
b15
The CiSIMKR register determines whether an interrupt request generated by completing a transmit/receive
operation in the corresponding message slot is enabled or disabled. When the SIMj bit (j = 0 to 15) is set to 1
(interrupt request enabled), an interrupt request generated by completing a transmit operation or a receive
operation in the corresponding message slot is enabled. Refer to 23.4 CAN Interrupts for details.
NOTES:
1. Set the CiSIMKR register while the CiMCTLj (j = 0 to 15) register of the corresponding message slot to the bit to be changed, is
2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock
set to 00h.
to the CAN module.
b8
b7
C0SIMKR and C1SIMKR Registers
b0
Bit Symbol
SIM15
SIM14
SIM13
SIM12
SIM11
SIM10
Symbol
C0SIMKR
C1SIMKR
SIM9
SIM8
SIM7
SIM6
SIM5
SIM4
SIM3
SIM2
SIM1
SIM0
Message slot 15
interrupt request mask bit
Message slot 14
interrupt request mask bit
Message slot 13
interrupt request mask bit
Message slot 12
interrupt request mask bit
Message slot 11
interrupt request mask bit
Message slot 10
interrupt request mask bit
Message slot 9
interrupt request mask bit
Message slot 8
interrupt request mask bit
Message slot 7
interrupt request mask bit
Message slot 6
interrupt request mask bit
Message slot 5
interrupt request mask bit
Message slot 4
interrupt request mask bit
Message slot 3
interrupt request mask bit
Message slot 2
interrupt request mask bit
Message slot 1
interrupt request mask bit
Message slot 0
interrupt request mask bit
Bit Name
Address
0211h - 0210h
0291h - 0290h
(1)
Controls whether an interrupt request of the
corresponding message slot is enabled or
masked.
0: Interrupt request masked (disabled)
1: Interrupt request enabled
Function
After Reset
0000h
0000h
23. CAN Module
(2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW