M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 385

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 361 of 587
Figure 22.30
Table 22.11
Ten low-order bits in the G2POi register Number of Pulses
00 0000 0000b
00 0000 0001b
00 0000 0010b
00 0000 0100b
00 0000 1000b
...
10 0000 0000b
6 low-order bits
in the base timer
i = 0 to 7
PO2iR bit: Bit in the register IIO3IR to IIO11IR
The above applies under the following conditions:
- In the G2POCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted)
- m = 1
6 low-order bits
in the base timer
OUTC2_i pin
Internal signal
G2POi register
OUTC2_i pin
PO2iR bit
Number of Modulated Pulses and Locations
Bit Modulation PWM Output Mode Operation
3Fh
00h
n
fBT2
3Fh
00h
n
n
1t
b15
n = 0 to 63 (3Fh)
Base width
"L" level
2t
n
b10 b9
0
1
2
4
8
...
512
3t
Number of modulated pulses
m = 0 to 1023 (3FFh)
Set to 0 by a program
inverse
511t
"L" level
512t
none
512t
256t, 768t
128t, 384t, 640t, 896t
64t, 192t, 320t, 448t, 576t, 704t, 832t, 960t
...
1t, 3t, 5t, 7t, ... 1019t, 1021t, 1023t
Repeat cycle
22. Intelligent I/O (Waveform Generation Function)
"L" width of m out of 1024 pulses is extended
by one fBT2 clock cycle
n+1
513t
b0
514t
Minimum resolution bit width
Set to 0 by a program
inverse
Location
1022t
1023t
1024t