M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 182

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 158 of 587
14.7
Figure 14.5
DMACII execution time is calculated by the following equations (single-speed mode):
Multiple transfers: t [bus clock] = 21+ (11 + b + c) × k
Other than multiple transfers: t [bus clock] = 6 + (26 + a + b + c + d) × m + (4 + e) × n
a: If IMM = 0 (source is immediate data), a = 0; if IMM = 1 (source is data in memory location), a = -1.
b: If UPDS = 1 (source address is incremented), b = 0; if UPDS = 0 (source address is fixed), b = 1.
c: If UPDD = 1 (destination address is incremented), c = 0; if UPDD = 0 (destination address is fixed), c = 1.
d: If OPER = 0 (calculation function is not selected), d = 0;
e: If CHAIN = 0 (chain transfer is not selected), e = 0; if CHAIN = 1 (chain transfer is selected), e = 4.
m: If BRST = 0 (single transfer), m = 1; if BRST = 1 (burst transfer), m = a value set in COUNT.
n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1.
k: The number of transfers set in bits CNT2 to CNT0 in MOD.
The above equations are approximations. The execution time varies depending on CPU state, bus wait states, and
DMACII index allocation.
The first instruction of the end-of-transfer interrupt routine is executed in the eighth bus clock after the DMACII
transfer is completed.
When a DMACII transfer request is generated simultaneously with another request having a higher priority (e.g.,
NMI or watchdog timer), the interrupt with higher priority is acknowledged first, and the pending DMACII transfer
starts after the interrupt sequence of the higher priority interrupt has been completed.
if OPER = 1 (calculation function is selected) and UPDS = 0 (source is immediate data or fixed address in
memory location), d = 7;
if OPER = 1 (calculation function is selected) and UPDS = 1 (source is incremented address in memory
location), d = 8.
Execution Time
Conditions of the example below:
Transfer counter = 2
Program
-memory-to-memory transfer (a = -1)
-incremented source address (b = 0)
-fixed destination address (c = 1)
-no calculation function (d = 0)
-no chain transfer (e = 0)
-single transfer (m = 1)
-the end-of-transfer interrupt (transfer counter = 2) occurs
DMACII transfer
requested
First DMACII transfer
Second DMACII transfer t = 6 + 26 x 1 + 4 x 0 = 32 bus clocks
Transfer Time
First
DMACII transfer
36 clocks
Transfer counter is decremented.
Transfer counter = 1
t = 6 + 26 x 1 + 4 x 1 = 36 bus clocks
Program
Transfer counter = 1
DMACII transfer
requested
Second
DMACII transfer
32 clocks
Transfer counter is decremented.
Transfer counter = 0
7 clocks
End-of-transfer interrupt
routine executed
14. DMACII