PIC16C770/P Microchip Technology, PIC16C770/P Datasheet - Page 123

• Manufacturer Part Number: PIC16C770/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770/P

• Program Memory Type: OTP
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3
The PIC16C717/770/771 devices have several differ-
ent RESETS. These RESETS are grouped into two
classifications; power-up and non-power-up. The
power-up type RESETS are the Power-on and Brown-
out Resets which assume the device V
normal operating range for the device’s configuration.
The non power-up type RESETS assume normal oper-
ating limits were maintained before/during and after the
RESET.
• Power-on Reset (POR)
• Programmable Brown-out Reset (PBOR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
FIGURE 12-4:
2002 Microchip Technology Inc.
MCLR
OSC1
V
DD
RESET
Dedicated
Oscillator
OST/PWRT
Programmable
V
Module
Brown-out
detect
WDT
DD
rise
OST
PWRT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Time-out
10-bit Ripple counter
Power-on Reset
10-bit Ripple counter
BODEN
External
RESET
SLEEP
DD
was below its
Enable PWRT
Enable OST
Some registers are not affected in any RESET condi-
tion. Their status is unknown on a Power-up Reset and
unchanged in any other RESET. Most other registers
are placed into an initialized state upon RESET, how-
ever they are not affected by a WDT Reset during
SLEEP, because this is considered a WDT Wake-up,
which is viewed as the resumption of normal operation.
Several status bits have been provided to indicate
which RESET occurred (see
Table 12-6 for a full description of RESET states of all
registers.
A simplified block diagram of the On-Chip Reset circuit
is shown in Figure 12-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
PIC16C717/770/771
S
R
DS41120B-page 121
Table 12-4).
Q
Chip_Reset
See