ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 126

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.7.5.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
– Set the TE bit to send a preamble of 10 (M = 0)
– Access the SCISR register and write the data to
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
This flag generates an interrupt if the TIE bit is set
and the I[|1:0] bits are cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
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and the SCIETPR registers.
or 11 (M = 1) consecutive ones (Idle Line) as first
transmission.
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
ter without overwriting the previous data.
Figure
1).
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
When a character transmission is complete (after
the stop bit) the TC bit is set and an interrupt is
generated if the TCIE is set and the I[1:0] bits are
cleared in the CCR register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break character length de-
pends on the M bit (see
As long as the SBK bit is set, the SCI sends break
characters to the TDO pin. After clearing this bit by
software, the SCI inserts a logic 1 bit at the end of
the last break character to guarantee the recogni-
tion of the start bit of the next character.
Idle Line
Setting the TE bit drives the SCI to send a pream-
ble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s
(idle line) before the first character.
In this case, clearing and then setting the TE bit
during a transmission sends a preamble (idle line)
after the current word. Note that the preamble du-
ration (10 or 11 consecutive ‘1’s depending on the
M bit) does not take into account the stop bit of the
previous character.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
Figure
2).