ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 183

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

beCAN CONTROLLER (Cont’d)
10.9.4.6 Bit Timing
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and re-
synchronizing on the following edges.
Its operation may be explained simply by splitting
nominal bit time into three segments as follows:
– Synchronization segment (SYNC_SEG): a bit
– Bit segment 1 (BS1): defines the location of the
Figure 105. Bit Timing
Figure 106. CAN Frames (Part 1of 2)
change is expected to occur within this time seg-
ment. It has a fixed length of one time quantum
(1 x t
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compen-
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
Inter-Frame Space
CAN
SYNC_SEG
).
1 x t
CAN
Arbitration Field
ID
12
Control Field
BIT SEGMENT 1 (BS1)
6
DLC
Data Frame (Standard identifier)
t
BS1
Data Field
NOMINAL BIT TIME
8 * N
44 + 8 * N
– Bit segment 2 (BS2): defines the location of the
– Resynchronization Jump Width (RJW): de-
To guarantee the correct behaviour of the CAN
controller, SYNC_SEG + BS1 + BS2 must be
greater than or equal to 5 time quanta.
For a detailed description of the CAN resynchroni-
zation mechanism and other bit timing configura-
tion constraints, please refer to the Bosch CAN
standard 2.0.
As a safeguard against programming errors, the
configuration of the Bit Timing Registers CBTR1
and CBTR0 is only possible while the device is in
Initialization mode.
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 time quanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
fines an upper bound to the amount of lengthen-
ing or shortening of the bit segments. It is
programmable between 1 and 4 time quanta.
SAMPLE POINT
CRC Field
CRC
16
BIT SEGMENT 2 (BS2)
Ack Field
2
t
BS2
Inter-Frame Space
or Overload Frame
EOF
7
TRANSMIT POINT
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