ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 195

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

beCAN CONTROLLER (Cont’d)
CAN RECEIVE FIFO REGISTERS (CRFR)
Read / Write
Reset Value: 0000 0000 (00h)
Note: To clear a bit in this register, software must
write a “1” to the bit.
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = RFOM Release FIFO Output Mailbox
- Read/Set
Set by software to release the output mailbox of
the FIFO. The output mailbox can only be released
when at least one message is pending in the FIFO.
Setting this bit when the FIFO is empty has no ef-
fect. If more than one message are pending in the
FIFO, the software has to release the output mail-
box to access the next message.
Cleared by hardware when the output mailbox has
been released.
Bit 4 = FOVR FIFO Overrun
- Read/Clear
This bit is set by hardware when a new message
has been received and passed the filter while the
FIFO was full.
This bit is cleared by software.
Bit 3 = FULL FIFO Full
- Read/Clear
Set by hardware when three messages are stored
in the FIFO.
This bit can be cleared by software writing a one to
this bit or releasing the FIFO by means of RFOM.
Bit 2 = Reserved. Forced to 0 by hardware.
Bits 1:0 = FMP[1:0] FIFO Message Pending
- Read
7
0
0
RFOM FOVR
FULL
0
FMP1 FMP0
0
These bits indicate how many messages are
pending in the receive FIFO.
FMP is increased each time the hardware stores a
new message in to the FIFO. FMP is decreased
each time the software releases the output mail-
box by setting the RFOM bit.
CAN INTERRUPT ENABLE REGISTER (CIER)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = WKUIE Wake-Up Interrupt Enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
Bits 6:4 = Reserved. Forced to 0 by hardware.
Bit 3 = FOVIE FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 2 = FFIE FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 1 = FMPIE FIFO Message Pending Interrupt
Enable
0: No interrupt on FMP[1:0] bits transition from 00b
1: Interrupt generated on FMP[1:0] bits transition
Bit 0 = TMEIE Transmit Mailbox Empty Interrupt
Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
WKUIE
to 01b.
from 00b to 01b.
7
0
0
0
FOVIE0
FFIE0
FMPIE0
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TMEIE
0