ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 174

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
beCAN CONTROLLER (Cont’d)
10.9.3.7 Loop Back combined with Silent Mode
It is also possible to combine Loop Back mode and
Silent mode by setting the LBKM and SILM bits in
the CDGR register. This mode can be used for a
“Hot Selftest”, meaning the beCAN can be tested
like in Loop Back mode but without affecting a run-
ning CAN system connected to the CANTX and
CANRX pins. In this mode, the CANRX pin is dis-
connected from the beCAN and the CANTX pin is
held recessive.
Figure 99. beCAN in Combined Mode
10.9.4 Functional Description
10.9.4.1 Transmission Handling
In order to transmit a message, the application
must select one empty transmit mailbox, set up
the identifier, the data length code (DLC) and the
data before requesting the transmission by setting
the corresponding TXRQ bit in the MCSR register.
Once the mailbox has left empty state, the soft-
ware no longer has write access to the mailbox
registers. Immediately after the TXRQ bit has
been set, the mailbox enters pending state and
waits to become the highest priority mailbox, see
Transmit Priority. As soon as the mailbox has the
highest priority it will be scheduled for transmis-
sion. The transmission of the message of the
scheduled mailbox will start (enter transmit state)
when the CAN bus becomes idle. Once the mail-
box has been successfully transmitted, it will be-
come empty again. The hardware indicates a suc-
cessful transmission by setting the RQCP and
TXOK bits in the MCSR and CTSR registers.
If the transmission fails, the cause is indicated by
the ALST bit in the MCSR register in case of an Ar-
174/265
beCAN
CANTX CANRX
Tx
=1
Rx
bitration Lost, and/or the TERR bit, in case of
transmission error detection.
Transmit Priority
By Identifier:
When more than one transmit mailbox is pending,
the transmission order is given by the identifier of
the message stored in the mailbox. The message
with the lowest identifier value has the highest pri-
ority according to the arbitration of the CAN proto-
col. If the identifier values are equal, the lower
mailbox number will be scheduled first.
By Transmit Request Order:
The transmit mailboxes can be configured as a
transmit FIFO by setting the TXFP bit in the CMCR
register. In this mode the priority order is given by
the transmit request order.
This mode is very useful for segmented transmis-
sion.
Abort
A transmission request can be aborted by the user
setting the ABRQ bit in the MCSR register. In
pending or scheduled state, the mailbox is abort-
ed immediately. An abort request while the mail-
box is in transmit state can have two results. If the
mailbox is transmitted successfully the mailbox
becomes empty with the TXOK bit set in the
MCSR and CTSR registers. If the transmission
fails, the mailbox becomes scheduled, the trans-
mission is aborted and becomes empty with
TXOK cleared. In all cases the mailbox will be-
come empty again at least at the end of the cur-
rent transmission.
Non-Automatic Retransmission Mode
To configure the hardware in this mode the NART
bit in the CMCR register must be set.
In this mode, each transmission is started only
once. If the first attempt fails, due to an arbitration
loss or an error, the hardware will not automatical-
ly restart the message transmission. At the end of
the first transmission attempt, the hardware con-
siders the request as completed and sets the
RQCP bit in the MCSR register. The result of the
transmission is indicated in the MCSR register by
the TXOK, ALST and TERR bits.