ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 204

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
beCAN CONTROLLER (Cont’d)
CAN FILTER MODE REGISTER (CFMR1)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:4 = Reserved. Forced to 0 by hardware.
Bit 3 = FMH5 Filter Mode High
Mode of the high registers of Filter 5.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 2 = FML5 Filter Mode Low
Mode of the low registers of filter 5.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 1 = FMH4 Filter Mode High
Mode of the high registers of filter 4.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 0 = FML4 Filter Mode Low
Mode of the low registers of filter 4.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
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7
0
0
0
0
FMH5 FML5 FMH4 FML4
0
FILTER x REGISTER[7:0] (CFxR[7:0])
Read / Write
Reset Value: Undefined
In all configurations:
Bits 7:0 = FB[7:0] Filter Bits
Identifier
Each bit of the register specifies the level of the
corresponding bit of the expected identifier.
0: Dominant bit is expected
1: Recessive bit is expected
Mask
Each bit of the register specifies whether the bit of
the associated identifier register must match with
the corresponding bit of the expected identifier or
not.
0: Don’t care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier
Note: Each filter x is composed of 8 registers,
CFxR[7:0]. Depending on the scale and mode
configuration of the filter the function of each reg-
ister can differ. For the filter mapping, functions
description and mask registers association, refer
to Section
A Mask/Identifier register in mask mode has the
same bit mapping as in identifier list mode.
Note: To modify these registers, the correspond-
ing FACT bit in the CFCR register must be
cleared.
FB7
must have the same level has specified in the
corresponding identifier register of the filter.
7
FB6
0.1.4.3 Identifier
FB5
FB4
FB3
Filtering.
FB2
FB1
FB0
0