ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 151

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN HEADER LENGTH REGISTER (LHLR)
Read Only
Reset Value: 0000 0000 (00 h).
Note: In LIN Slave mode when LASE = 1 or LHDM
= 1, the LHLR register is accessible at the address
of the SCIERPR register.
Otherwise this register is always read as 00h.
Bits 7:0 = LHL[7:0] LIN Header Length.
This is a read-only register, which is updated by
hardware if one of the following conditions occurs:
- After each break detection, it is loaded with
“FFh”.
- If a timeout occurs on T
00h.
- After every successful LIN Header reception (at
the same time than the setting of LHDF bit), it is
loaded with a value (LHL) which gives access to
the number of bit times of the LIN header length
(T
below:
LHL Coding:
T
LHL(7:2) represents the mantissa of (57 - T
ER
LHL(1:0) represents the fraction (57 - T
LHL7
HEADER_MAX
LHL[7:2]
HEADER
)
7
3Ah
3Bh
3Eh
3Fh
39h
0h
1h
...
...
LHL6
). The coding of this value is explained
LHL5
(57 -
= 57
Mantissa
T
HEADER
56
57
58
62
63
LHL4
...
...
0
1
HEADER
LHL3
)
LHL2
, it is loaded with
Never Occurs
Never Occurs
(
Initial value
T
Mantissa
HEADER
LHL1
57
56
HEADER
...
...
1
0
HEAD-
)
LHL0
0
)
Example of LHL coding:
Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
This leads to:
Mantissa (57 - T
Fraction (57 - T
Therefore:
(57 - T
and T
Example 2:
57 - T
LHL(1:0) = rounded(4*0.21d) = 1d
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
Therefore LHL(7:0) = 10010001 = 91h
Example 3:
57 - T
LHL(1:0) = rounded(4*0.90d) = 4d
The carry must be propagated to the matissa:
LHL(7:2) = Mantissa (36.90d) + 1 = 37d =
Therefore LHL(7:0) = 10110000 = A0h
LHL[1:0]
HEADER
HEADER
HEADER
HEADER
0h
1h
2h
3h
= 44.25d
= 36.21d
= 36.90d
) = 12.75d
HEADER
HEADER
Fraction (57 -
) = 3/4 = 0.75
) = 12d
1/4
1/2
3/4
0
T
HEADER
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)