ST10F276-6Q3 STMicroelectronics, ST10F276-6Q3 Datasheet - Page 217

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ST10F276-6Q3

Manufacturer Part Number
ST10F276-6Q3
Description
MCU 16BIT 832K FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F276-6Q3

Core Processor
ST10
Core Size
16-Bit
Speed
64MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
ST10F276E
Figure 65. CLKOUT and READY
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
7. The next external bus cycle may start here.
CLKOUT
ALE
RD, WR
Synchronous
READY
Asynchronous
READY
LOW at this sampling point terminates the currently running bus cycle.
WR).
CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t
synchronized. This is guaranteed if READY is removed in response to the command (see Note 4).
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles; for a demultiplexed bus
without MTTC wait state this delay is zero.
t
t
58
32
(3)
t
t
t
59
30
34
Running cycle
(2)
t
t
33
31
t
t
35
58
(3)
(1)
t
37
(3)
t
t
36
59
t
(5)
29
t
35
wait state
READY
(3)
t
36
37
in order to be safely
Electrical characteristics
MUX / Tri-state
t
60
(4)
(6)
(6)
7)
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