ST10F276-6Q3 STMicroelectronics, ST10F276-6Q3 Datasheet - Page 68

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ST10F276-6Q3

Manufacturer Part Number
ST10F276-6Q3
Description
MCU 16BIT 832K FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F276-6Q3

Core Processor
ST10
Core Size
16-Bit
Speed
64MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Bootstrap loader
5.6.9
5.6.10
5.6.11
68/231
The values for operand0, operand1 and the signature should be such that the sequence
shown in the figure below is successfully executed.
Alternate boot user software aspects
User defined alternate boot code must start at 09’0000h. A new SFR created on the
ST10F276E indicates that the device is running in Alternate Boot Mode: Bit 5 of EMUCON
(mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration.
All the other bits are ignored when checking the content of this register to read the value of
bit 5.
This bit is a read-only bit. It remains set until the next software or hardware reset.
EMUCON register
EMUCON (FE0Ah / 05h)
Table 36.
Internal decoding of test modes
The test mode decoding logic is located inside the ST10F276E Bus Controller.
The decoding is as follows:
The other configurations select ST internal test modes.
15
MOV
ADD
CPLB
CMP
Alternate Boot Mode decoding: (P0L.5 & P0L.4)
Standard Bootstrap decoding: (P0L.5 & P0L.4)
Normal operation: (P0L.5 & P0L.4)
ABM
Bit
14
Rx, CheckBlock1Addr; 00’0000h for standard reset
Rx, CheckBlock2Addr; 00’1FFCh for standard reset
RLx
Rx, CheckBlock3Addr; 00’1FFEh for standard reset
ABM bit description
13
ABM Flag (or TMOD3)
0: Alternate Boot Mode is not selected by reset configuration on P0L[5..4]
1: Alternate Boot Mode is selected by reset configuration on P0L[5..4]: This bit is
set if P0L[5..4] = ‘01’ during hardware reset.
12
11
-
-
10
9
; 1s complement of the lower
; byte of the sum
SFR
8
7
Function
6
ABM
R
5
4
3
Reset value: - xxh:
2
-
ST10F276E
1
0

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