ST10F276-6Q3 STMicroelectronics, ST10F276-6Q3 Datasheet - Page 28

• Manufacturer Part Number: ST10F276-6Q3
• Description: MCU 16BIT 832K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276-6Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Internal Flash memory
Note:
4.2.5
4.3
4.3.1
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bank, or from the other module or again from another memory (internal RAM or external
memory).
During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the
Flash Control Registers.
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal
voltage threshold, any write operation running is suddenly interrupted and the modules are
reset to Read mode. At following Power-on, an interrupted Flash write operation must be
repeated.
Registers description
Flash control register 0 low
The Flash control register 0 low (FCR0L) together with the Flash control register 0 high
(FCR0H) is used to enable and to monitor all the write operations for both the Flash
modules. The user has no access in write mode to the test-Flash (B0TF). Besides, test-
Flash block is seen by the user in Bootstrap mode only.
FCR0L (0x0E 0000)
Table 6.
15
BSY(3:2)
Bit
14
Flash control register 0 low
13
Bank 3:2 Busy (XFLASH)
These bits indicate that a write operation is running on the corresponding bank of
XFLASH. They are automatically set when bit WMS is set. Setting Protection
operation sets bit BSY2 (since protection registers are in the Block B2). When these
bits are set every read access to the corresponding bank will output invalid data
(software trap 009Bh), while every write access to the bank will be ignored. At the end
of the write operation or during a Program or Erase Suspend these bits are
automatically reset and the bank returns to read mode. After a Program or Erase
Resume these bits are automatically set again.
12
Reserved
11
10
9
FCR
8
7
Function
BSY1 BSY0 LOCK Res. BSY3 BSY2 Res.
R
6
R
5
R
4
3
Reset value: 0000h
R
2
ST10F276E
R
1
0