ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 121

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Note Reading the upper half of the Control
15.4 - CAN Interrupt Handling
The on-chip CAN Module has one interrupt
output,
synchronization stage) to a standard interrupt
node in the ST10F280 in the same manner as all
other
peripherals. The control register for this interrupt
is XP0IC (located at address F186h/C3h for CAN1
and F18Eh/C7h for CAN2 in the ESFR range).
The associated interrupt vector is called XP0INT
at location 100h (trap number 40h) and XP1INT at
location 104h (trap number 41h). With this
configuration, the user has all control options
available for this interrupt, such as enabling/
disabling, level and group priority, and interrupt or
PEC service (see note below).
As for all other interrupts, the interrupt request flag
XP0IR/XP1IR in register XP0IC/XP1IC is cleared
automatically by hardware when this interrupt is
serviced (either by standard interrupt or PEC ser-
vice).
Note As a rule, CAN interrupt requests can be
EWRN
RXOK
TXOK
BOFF
Bit
Register (status partition) will clear the
Status Change Interrupt value in the
Interrupt Register, if it is pending. Use byte
accesses to the lower half to avoid this.
serviced by a PEC channel. However,
because PEC channels only can execute
interrupts
which
Transmitted Message Successfully
Indicates that a message has been transmitted successfully (error free and acknowledged by at least one
other node), since this bit was last reset by the CPU (the CAN controller does not reset this bit!).
Received Message Successfully
Indicates that a message has been received successfully, since this bit was last reset by the CPU (the CAN
controller does not reset this bit!).
Error Warning Status
Indicates that at least one of the error counters in the EML has reached the error warning limit of 96.
Busoff Status
Indicates when the CAN controller is in busoff state (see EML).
is
of
connected
the
standard
(through
on-chip
Function (Control Bit)
a
Since an interrupt request of the CAN Module can
be generated due to different conditions, the
appropriate CAN interrupt status register must be
read in the service routine to determine the cause
of the interrupt request. The Interrupt Identifier
INTID (a number) in the Interrupt Register
indicates the cause of an interrupt. When no
interrupt is pending, the identifier will have the
value 00h. If the value in INTID is not 00h, then
there is an interrupt pending. If bit IE in the Control
Register is set, also the interrupt line to the CPU is
activated. The interrupt line remains active until
either INTID gets 00h (after the interrupt requester
has been serviced) or until IE is reset (if interrupts
are disabled).
The interrupt with the lowest number has the
highest priority. If a higher priority interrupt (lower
number) occurs before the current interrupt is
processed, INTID is updated and the new
interrupt overrides the last one. The Table 28 lists
the valid values for INTID and their corresponding
interrupt sources.
single predefined data transfers (there are
no conditional PEC transfers), PEC service
can only be used, if the respective request
is known to be generated by one specific
source, and that no other interrupt request
will be generated in between. In practice
this seems to be a rare case.
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