ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 87

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ST10F280

Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F280

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure is slightly dif-
ferent (see figure Figure 37). After reset the BHE or WRH function must be used depending on the sys-
tem start-up configuration. In either of these cases, there is no possibility to program any port latches
before. Thus, the appropriate alternate function is selected automatically. If BHE/WRH is not used in the
system, this pin can be used for general purpose I/O by disabling the alternate function (BYTDIS = ‘1’ /
WRCFG=’0’).
Figure 37 : Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH)
Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit
12.6 - Port 4
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corre-
sponding direction register DP4.
P4 (FFC8h / E4h)
P4.y
15
-
Bit
DP3.12=’1’ is not required.
During bus hold, pin P3.12 is switched back to its standard function and is then controlled by
DP3.12 and P3.12. Keep DP3.12 = ’0’ in this case to ensure floating in hold mode.
14
-
Read DP3.x
Write DP3.x
Port Output
Write P3.x
Read P3.x
13
Direction
-
Latch
Latch
Port data register P4 bit y
12
-
11
-
MUX
10
-
Alternate
Data
Output
1
0
Alternate
Function
Enable
“1”
9
-
8
-
1
0
1
0
SFR
MUX
MUX
P4.7
RW
7
Function
P4.6
RW
CPU Clock
6
Latch
Input
P4.5
RW
5
Output
Buffer
P4.4
RW
4
P4.3
RW
3
Reset Value: - - 00h
P4.2
RW
2
x = 15, 12
P3.12/BHE
P3.15/CLKOUT
ST10F280
P4.1
RW
1
87/186
P4.0
RW
0

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