ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 68

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
11.2.3 - Interrupt Request Generation
Each of the four channels of the XPWM module can generate an individual interrupt request. Each of
these “channel interrupts” can activate the common “module interrupt”, which actually interrupts the CPU.
This common module interrupt is controlled by the XPWM Module Interrupt Control register XP2IC( Xpe-
ripherals 2 control register). The interrupt service routine can determine the active channel interrupt(s)
from the channel specific interrupt request flags PIRx in register XPWMCON0. The interrupt request flag
PIRx of a channel is set at the beginning of a new PWM cycle, i.e. upon loading the shadow registers.
This indicates that registers XPPx and XPWx are now ready to receive a new value. If a channel interrupt
is enabled via its respective PIEx bit, also the common interrupt request flag XP2IR in register XP2IC is
set, provided that it is enabled via the common interrupt enable bit XP2IE.
Note: The channel interrupt request flags (PIRx in register XPWMCON0) are not automatically cleared
XP2IC (F196h / CBh)
Note: Refer to the general Interrupt Control Register description for an explanation of the control fields.
11.2.4 - XPWM Output Signals
The output signals of the four XPWM channels are XPWM3...XPWM0. The output signal of each PWM
channel is individually enabled by control bit PENx in register XPWMCON1.
The XPWM signals are XORed with the outputs of the register XPOLAR(3...0) before being driven to the
output pins. This allows driving the XPWM signal directly to the output pin (XPOLAR.x=’0’) or driving the
inverted XPWM signal (XPOLAR.x=’1’).
Figure 24 : XPWM Output Signal Generation
68/186
PWM 3
PWM 2
PWM 1
PWM 0
15
-
by hardware upon entry into the interrupt service routine, so they must be cleared via software.
The module interrupt request flag XP2IR is cleared by hardware upon entry into the service
routine, regardless of how many channel interrupts were active. However, it will be set again if
during execution of the service routine a new channel interrupt request is generated.
14
-
13
-
12
-
XPWMCON1.PEN0
XPWMCON1.PEN3
XPWMCON1.PEN2
XPWMCON1.PEN1
11
-
&
10
-
9
-
XPWMCON1.PB01
8
-
ESFR
XP2IR XP2IE
RW
7
RW
6
Latch XPOLAR.0
Latch XPOLAR.1
Latch XPOLAR.3
Latch XPOLAR.2
5
4
ILVL
RW
3
Reset Value: - - 00h
2
Pin XPWM3
Pin XPWM2
Pin XPWM1
Pin XPWM0
1
GLVL
RW
0