ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 81

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

P2 (FFC0h / E0h)
DP2 (FFC2h / E1h)
ODP2 (F1C2h / E1h)
12.4.1 - Alternate Functions of Port 2
All Port 2 lines (P2.15...P2.0) serve as capture
inputs or compare outputs (CC15IO...CC0IO) for
the CAPCOM1 unit.
When a Port 2 line is used as a capture input, the
state of the input latch, which represents the state
of the port pin, is directed to the CAPCOM unit via
the line “Alternate Pin Data Input”. If an external
capture trigger signal is used, the direction of the
respective pin must be set to input. If the direction
is set to output, the state of the port output latch
will be read since the pin represents the state of
the output latch. This can be used to trigger a cap-
ture event through software by setting or clearing
the port latch. Note that in the output configura-
tion, no external device may drive the pin, other-
wise conflicts would occur.
ODP2
P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9
P2.y
DP2.y
ODP2.y
DP2.
RW
RW
RW
.15
15
15
15
15
ODP2
Bit
Bit
Bit
DP2.
RW
RW
RW
.14
14
14
14
14
ODP2
DP2.
RW
RW
RW
.13
13
13
13
13
Port data register P2 bit y
Port direction register DP2 bit y
DP2.y = 0: Port line P2.y is an input (high-impedance)
DP2.y = 1: Port line P2.y is an output
Port 2 Open Drain control register bit y
ODP2.y = 0: Port line P2.y output driver in push/pull mode
ODP2.y = 1: Port line P2.y output driver in open drain mode
ODP2
DP2.
RW
RW
RW
.12
12
12
12
12
ODP2
DP2.
RW
RW
RW
.11
11
11
11
11
ODP2
DP2.
RW
RW
RW
.10
10
10
10
10
DP2.9 DP2.8 DP2.7 DP2.6 DP2.5 DP2.4 DP2.3 DP2.2 DP2.1 DP2.0
ODP2
RW
RW
RW
.9
9
9
9
ODP2
P2.8
RW
RW
RW
.8
8
8
8
ESFR
SFR
SFR
ODP2
P2.7
RW
RW
RW
.7
When a Port 2 line is used as a compare output
(compare modes 1 and 3), the compare event (or
the timer overflow in compare mode 3) directly
effects the port output latch. In compare mode 1,
when a valid compare match occurs, the state of
the port output latch is read by the CAPCOM con-
trol hardware via the line “Alternate Latch Data
Input”, inverted, and written back to the latch via
the line “Alternate Data Output”.
The port output latch is clocked by the signal
“Compare Trigger” which is generated by the
CAPCOM unit. In compare mode 3, when a match
occurs, the value '1' is written to the port output
latch via the line “Alternate Data Output”. When
an overflow of the corresponding timer occurs, a
'0' is written to the port output latch. In both cases,
the output latch is clocked by the signal “Compare
Trigger”.
7
7
7
Function
Function
Function
ODP2
P2.6
RW
RW
RW
.6
6
6
6
ODP2
P2.5
RW
RW
RW
.5
5
5
5
ODP2
P2.4
RW
RW
RW
.4
4
4
4
ODP2
P2.3
RW
RW
RW
.3
3
3
3
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0000h
ODP2
P2.2
RW
RW
RW
.2
2
2
2
ODP2
ST10F280
P2.1
RW
RW
RW
.1
1
1
1
ODP2
81/186
P2.0
RW
RW
RW
.0
0
0
0