ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 163

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes f
locked on f
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 78 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation D
Figure 78 : Approximated Maximum PLL Jitter
20.4.8 - External Clock Drive XTAL1
V
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input
Oscillator period
High time
Low time
Rise time
Fall time
DD
= 5V
frequency when using an external crystal oscillator. Howevwer, 40MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels V
Parameter
±4
±3
±2
±1
Max.jitter [%]
TCL
XTAL
10%, V
MIN
2
D
. The relative deviation of TCL is
N
=
=
4
SS
TCL
4 N 15 %
= 0V, T
t
t
t
t
t
OSC
1
2
3
4
Symbol
–
NOM
N
:
SR
SR
SR
SR
SR
A
8
= -40 to +125 °C




1
–
CPU
min
25
10
10
-------------
100
f
D N
–
–
CPU
1
2
2
to keep it




= f
XTAL
16
max
3
3
–
–
–
2
2
IL
and V
IH2
This approximated formula is valid for
1
f
where N = number of consecutive TCL periods
and 1
(N = 3):
D
3 TCL
3 TCL
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible.
12.5
min
CPU
5
5
–
–
.
3
2
2
N
= f
min
min
XTAL
40 and 10MHz
N
max
3
3
–
–
–
/ 2
3
2
40. So for a period of 3 TCL periods
=
=
=
=
F = 2 / 2.5 / 3 / 4 / 5 / 10
4 - 3/15 = 3.8%
3 TCL
3 TCL
(36.075ns at f
40 x N
10
10
min
f
CPU
–
–
2
2
NOM
NOM
f
CPU
= f
32
XTAL
x (1 - 3.8/100)
x 0.962
N
100 x N
CPU
40MHz.
max
x F
3
3
–
–
2
2
= 40MHz)
ST10F280
163/186
Unit
ns
ns
ns
ns
ns